|Username||Post: The Daily Activist Stock for 03/15/2008 is Synplicity|
03-16-08 01:30 PM - Post#206
Filed with the SEC from Feb 28 to Mar 05:
Investor J. Carlo Cannell sent a letter to Synplicity requesting that the company hire an investment banker to solicit its sale. Cannell currently owns 1,700,967 shares (6.4%).
We are a leading provider of software products that enable the rapid and effective design and verification of large, complex semiconductors used in networking and communications, military and aerospace, semiconductor, consumer, computer and peripheral, and other electronics systems. Our software products perform essential steps in the process of designing and verifying semiconductors that are tailored to perform a specific function including field programmable gate arrays (“FPGAs”). We employ proprietary logic synthesis, physical synthesis and debug technology to simplify, improve and accelerate the design and verification of large complex FPGAs and ASICs. We believe our semiconductor design software products, coupled with our responsive customer support, assist our customers in meeting their performance goals and in reducing their time to market for their electronic systems.
Manufacturers of networking and communications, military and aerospace, semiconductor, consumer, computer and peripheral, and other electronics systems utilize a wide variety of advanced semiconductors, including FPGAs and ASICs, in their products. Unlike off the shelf standard function semiconductors, FPGAs and ASICs are tailored to perform specific functions defined by electronic product designers. FPGAs are semiconductors that are customized or programmed to perform a specific function after the semiconductors are manufactured, whereas ASICs are customized during the manufacturing process.
FPGAs and ASICs are used to implement proprietary intellectual property and to provide the equipment manufacturer’s products with enhanced performance, flexibility and differentiation. FPGAs provide equipment manufacturers with the ability to create and modify semiconductor designs quickly and easily. With FPGAs, electronics manufacturers can make changes to the design even after the customer uses the product. This ease of creation and modification helps electronics manufacturers meet time to market requirements by shortening development times. In this respect, FPGAs provide electronic equipment manufacturers the ability to get to market quickly and the flexibility to update their products to address rapidly changing industry and interoperability standards. ASICs, on the other hand, can achieve higher performance, lower power consumption and lower unit cost than FPGAs when produced in volume. However, ASICs generally have a longer development cycle, as well as lengthy and expensive custom fabrication processes prior to shipment.
The capacity of FPGAs and ASICs on average has increased due to advanced manufacturing processes. These advanced manufacturing processes help improve performance, lower overall part costs and further expand the breadth of applications for which FPGA and ASIC semiconductors can be used.
Challenges of designing FPGAs and ASICs
As more complex FPGAs and ASICs with higher capacity are used in the design of electronic equipment, these FPGAs and ASICs often require significant resources to design and test their functionality. Large semiconductor designs require more time to develop and test, which may limit the equipment manufacturer’s ability to get to market quickly.
FPGAs and ASICs are increasingly incorporating digital signal processing (“DSP”) functionality to obtain a substantial performance increase over standard DSP processors. However, an obstacle in implementing DSP functionality in FPGAs is that it is a very time-consuming process to explore different design architectures in order to achieve optimal performance. Traditional techniques for converging on a solution use very iterative and manual methods that frequently do not produce optimal results.
Complex ASIC design, using the traditional cell-based library approach for implementation, has become increasingly costly as deep submicron process technologies required larger investments for EDA tools, design resources and initial semiconductor manufacturing costs. In addition to rising costs, the time it takes to complete a typical cell-based ASIC has lengthened as the verification process has become increasingly difficult. These and other economic forces have resulted in a declining number of cell-based ASIC design starts over the past nine years.
Electronic product designers seek design solutions that produce high-performance designs, increase productivity, reduce costs and are easy to learn and use. To achieve these objectives, electronic product designers, including equipment manufacturers using FPGAs and ASICs, have recognized the advantage of certain software solutions which address critical steps in the development cycle.
To date, these software solutions have focused on several functions in the development cycle including:
Logic synthesis . Logic synthesis software compiles a high level textual description of the desired function of a semiconductor into an optimized network of elements, each of which is known as a logic or memory element. Because the logic and memory elements must interact and exhibit high performance, logic synthesis is critical to reduce the number of required components and improve the frequency at which the semiconductor can be operated.
Physical synthesis . Physical synthesis software combines the function of logic synthesis software with some of the functions of placement and routing software. Placement and routing software processes the optimized description of the semiconductor created by logic synthesis to place the logic
and memory elements in locations on the semiconductor and to assign routes for wires between those placed elements. The goal is to keep wires short in order to maximize performance. Because a physical synthesis system controls the locations of elements, it can identify performance limitations more easily and fix them with a combination of placement changes and logic synthesis optimizations.
Verification . Verification software uses the information from the functions and integrity of the semiconductor to test whether it will perform as intended. For example, with ASICs, the designer must verify whether the semiconductor will perform as intended and whether the proposed design works with other components in the electronics system, such as software or a communication module. Mistakes not identified prior to ASIC chip manufacture are costly and can require weeks or months for correction.
Our Software Solutions
Our software solutions improve performance and shorten development times for complex FPGAs and ASICs by simplifying, improving and automating key design planning, logic synthesis, physical synthesis and verification functions. Our products utilize a number of sophisticated mathematical algorithms, electrical engineering techniques and advanced software operations.
A key feature of our products is the ability to generate and display concurrently four views of a semiconductor design—the textual design description, a highly abstract graphical representation of the design description, an optimized, detailed diagram showing the various elements of the semiconductor design and a physical representation of the design elements. As the designer changes the textual description, the other three views automatically highlight the selected areas of the design. These alternate representations allow the designer to manipulate and optimize the design and diagnose problems. Our software products also provide the following features and benefits to our customers and their electronic product designers:
Accelerated time to market . Electronic product designers require time efficient solutions. Our products optimize small designs in seconds and large designs in minutes or hours, which we believe is faster than alternative software. Reduced execution time shortens time to market because logic synthesis, physical synthesis and verification are typically performed repeatedly during the design process. In addition, our physical synthesis products produce design results that correlate well with the completed physical design, thus reducing the number of design iterations typically required with design tools that use less accurate statistical wire length models.
Ease of use . Our products are designed to be easy to install, learn and use. The user enters only information that is specific to the design. Our products employ complex algorithms, but their sophistication makes the designers’ work simpler. We believe both experienced and novice users value our products because they provide highly optimized designs that require a minimum level of design tool specific effort. We believe our solutions’ ease of use and graphical representations make them accessible to a larger group of designers without sacrificing quality of results or achievement of design goals. Our design tools have the added benefit of reducing the amount of technical support required to assist customers in tool use. Our technical support resources can focus on more design related support, which is of more value to customers.
Design goal achievement. Our products enable designers to design products quickly that meet or exceed their semiconductor performance and capacity utilization goals. Efficient and cost-effective manufacturing of a semiconductor depends on full utilization of the semiconductor’s capacity. Users specify design constraints through our graphical user interface and then use our products to automatically process the design to achieve function, performance and capacity goals. The complex optimization operations that our products perform employ the most advanced features of the target semiconductor and result in a highly optimized design that improves performance of the electronic equipment. Our solutions may also enable designers to use less costly semiconductors to achieve the same performance goals, thus reducing end system costs.
Comprehensive customer support . Because of the complex nature of our customers’ design activities, we believe our support services are valuable to our customers. We emphasize rapid resolution of customer questions by staffing our customer support operation with knowledgeable personnel. We have provided our customer service organization with sufficient resources to assist our staff in responding to customer problems, often within 24 hours. We also make available through our web site information regarding support solutions, problem submission and problem status.
In March 2006, one of our three partners serving the Structured ASIC and ASIC synthesis markets announced its decision to cease further development of its semiconductor product for which our software product was designed specifically and exclusively. After this announcement, we evaluated the impact of this decision and other factors and decided to exit the Structured ASIC and ASIC synthesis markets (the “ASIC products”) and to refocus our efforts on our core competencies in our FPGA synthesis, DSP synthesis and ASIC verification product lines. As a result, we eliminated certain positions in engineering and sales and marketing and reassigned various employees, principally in engineering, from ASIC to other areas where we perceive positive growth opportunities and wrote off capitalized software development costs related to the ASIC products. We have ceased to offer the ASIC products to customers while we continue to support existing customers who had previously purchased our products. Our support will continue on a declining basis through the middle of 2008. Our revenue from the ASIC products substantially declined in 2006 when compared to 2005 and will continue to decline through the remaining support period. Issues resulting from the decision noted above are further discussed in Management’s Discussion and Analysis of Financial Condition and Results of Operations as well as in our Notes to Consolidated Financial Statements.
We believe our products are easier to use and produce superior results more rapidly than alternative solutions. In addition, our core technology platform enables us to produce innovative products quickly. Selected features of our technology include:
Behavior Extracting Synthesis Technology
Our products are designed with our proprietary technology to recognize and locate common circuit building blocks within designs and maintain high-level representations of these blocks throughout the synthesis process. Other synthesis products use circuit representations that maintain detailed level representations of the design, but lose important information. By maintaining behavioral information that describes a semiconductor’s function throughout synthesis, we believe our synthesis products make better overall optimizations, which result in better circuit performance.
Physical synthesis innovations . Achieving superior performance in large FPGAs requires solving specialized problems not encountered in standard cell ASICs. We have patented our algorithms that solve many of these problems. These algorithms involve combining synthesis with processes that are normally applied later in the semiconductor design process, a combination referred to as physical synthesis. We believe our physical synthesis innovations enable us to achieve very tight correlation between our estimated results and the actual results, thereby reducing design iterations.
Graph-based Physical Synthesis. Synplicity invented graph-based physical synthesis to enable a single-pass physical synthesis flow for 90nm and below FPGAs. FPGAs require a new approach to physical synthesis because the methods developed earlier for ASIC physical synthesis do not work for FPGAs. The situation arises because in ASICs, physical proximity implies better timing. This is not the case in FPGAs. The essence of our approach is that the pre-existing wires, switches and placement sites used for routing an FPGA can be represented as a detailed routing resource graph. Using this representation, our graph-based physical synthesis merges optimization, placement and routing to ensure available, fast routes along critical paths. This technology generates a fully placed and physically optimized netlist as output ready for the FPGA vendor’s routing tool.
Fast, memory efficient algorithms . Long run times are a commonly encountered barrier to processing large designs. Because synthesis is performed repeatedly during the design process, fast run times are an important time-to-market determinant. All of the algorithms employed in our products were carefully selected and implemented for fast run times and efficient memory utilization. These algorithms’ run times increase linearly as design size increases, as opposed to nonlinearly with other software products.
Embedded electrical engineering knowledge . Synthesis and optimization of complex circuits are accomplished through a large collection of algorithms and heuristics. For any given circuit, the application of these algorithms requires many decisions, including which algorithms to use and in what order to apply them. Implementing a synthesis product is considerably easier if the user is required to make these types of decisions. However, this places the burden of understanding the effects of synthesis algorithms on the user and results in a product that is difficult to use. Instead, we build products with a high level of automation for making these decisions by embedding a high degree of electrical engineering knowledge in the products so that optimization decisions are performed automatically.
Prototyping and Debug . Complex ASIC designs often cannot be adequately verified except with a prototype that operates close to the intended operating speed of the ASIC. We have developed patented technology and products that assist in the implementation of fast prototypes of ASICs, helping the designer implement the ASIC functionality on a set of FPGAs. Once the prototype is in place, understanding the operation of the circuit is often the critical path to success. We have technology and products that help the designer debug a circuit by relating the actual operation of the circuit back to the HDL input used to implement the circuit.
Synplify and Synplify Pro Products
In 1995, we introduced Synplify, our logic synthesis product that enables customers to implement their designs in FPGAs quickly and easily. In May 2000, we launched Synplify Pro, our advanced FPGA logic synthesis product incorporating improved productivity features and offering enhanced results. To perform logic synthesis, our Synplify and Synplify Pro products employ proprietary optimization algorithms. Our Synplify and Synplify Pro products take advantage of specialized features provided by the FPGA manufacturers that improve performance for a particular design. Logic synthesis software products transform a high level design specification into a format comprised of logic elements and wires interconnecting those elements that is ready for implementation in a semiconductor. Logic synthesis is a primary determinant of design performance. As a result, logic synthesis has a significant impact on the overall performance of the electronic system in which the FPGA resides. We believe that our Synplify and Synplify Pro products produce the industry’s highest performance results on the basis of speed and capacity utilization of the resulting FPGA.
Because logic synthesis is performed multiple times during the design process, the less time synthesis requires, the quicker the engineer can complete the design process. We believe our Synplify and Synplify Pro products have the industry’s fastest run times. We employ algorithms that scale linearly in run time with the size of the design. Small designs can be synthesized in seconds and designs for the newest, largest FPGAs can be synthesized in hours or even minutes. Synplify and Synplify Pro require only the input of readily available design data. This information is entered via a user friendly graphical user interface, which allows designers to specify all design constraints in a single location quickly.
Synplify Premier Product
Synplicity’s Synplify Premier software, introduced in late 2005, builds upon Synplicity’s industry leading synthesis technology and adds new graph-based physical synthesis and real-time simulator-like visibility into operating FPGA devices. Synplicity invented graph-based physical synthesis to improve timing closure by means of a single-pass physical synthesis flow for 90nm and below FPGAs. The Synplify Premier tool’s graph-based physical synthesis technology merges optimization and placement and routing to generate a fully placed and physically optimized netlist, providing rapid timing closure and a 5% to 20% timing improvement. In addition, the Synplify Premier product offers an efficient method of in-system verification of FPGAs. The Synplify Premier software dramatically accelerates the debug process and provides a rapid and incremental method for finding elusive design problems.
In November 2002, we acquired a key RTL debug product from Bridges2Silicon, Inc. which we introduced under a new Synplicity product name, Identify. This product allows engineers to debug their FPGAs directly from their RTL source code during chip operation. Identify’s efficient method of functional hardware debug helps engineering teams avoid what would otherwise be a tedious and costly debug using hardware analyzers.
Our Identify product allows FPGA designers and ASIC prototyping designers to functionally debug their hardware directly in their RTL source code. This allows functional verification with RTL designs 10,000 times faster than today’s RTL simulators and enables the use of in-system stimulus for applications-like networking, audio and video and hardware/software co-development. With Identify, designers directly select signals and conditions in their RTL source code. The actual values of these signals in the hardware can then be viewed in the original RTL, based on the conditions the user created.
Synplify DSP Product
In July 2004, we introduced Synplify DSP, our first Electronic System Level (ESL) synthesis product created to bridge between system level DSP design and analysis and semiconductor hardware design. Synplify DSP performs high-level DSP optimizations from a Simulink specification. These special DSP optimizations allow designers to capture the behavior needed for their DSP algorithm without concern for the specific hardware implementation. Synplify DSP automatically produces a highly optimized, technology independent implementation of the design ready for RTL synthesis.
DSP designers are increasingly targeting FPGA hardware for implementation of their high-performance DSP designs. FPGAs can achieve a performance of hundreds of millions of operations per second, which far exceeds the performance available in more traditional DSP processors. Today’s FPGAs also contain large quantities of DSP blocks and multipliers, facilitating efficient and parallel implementation of DSP functions in programmable logic. Until the introduction of Synplify DSP, there had been no automated way to get a design specified at the algorithm level from tools such as Simulink ® by The MathWorks, into high-quality RTL, architecture independent code suitable for semiconductor implementation. A common implementation path had been to hand-code the RTL with numerous iterations between the DSP algorithm architect and the RTL hardware designer, which is error prone and time consuming. We believe Synplify DSP offers the only automated way to fully optimize DSP design expressed in the SimuLink environment into vendor independent RTL code suitable for FPGA or ASIC implementation.
ASIC Verification Solution
In 1999, we introduced Certify, a software product for the verification of ASICs using prototypes consisting of multiple FPGAs. Our Certify product enables ASIC design teams to create hardware prototypes early in the design process when design changes are easier and less costly. Certify also assists customers in verifying that the final system will work as specified, will work with system level software and will meet customer requirements. Customers who use our Certify product to define their prototypes can begin system integration, software verification, chip and system verification and end customer validation earlier than other approaches to functional verification. Certify can process multimillion gate designs in a single pass without the complex scripts commonly required by ASIC synthesis products. We believe Certify is the only product that processes ASIC designs and produces multi-FPGA prototypes at the RTL level, enabling rapid iterations of the prototype during the verification stage.
Our Certify product is a verification product incorporating synthesis and enabling the user to create prototypes automatically from the user’s textual design specification. The ability to operate the prototype at or near the speed of the final product can be very important for ASIC verification. Other available approaches, such as logic simulation software, emulation systems or reconfigurable prototyping systems, cannot run at a sufficient performance level for many applications, such as mobile telephony, optical switching or streaming video in real time. Our Certify product enables designers to create FPGA-based prototypes that operate at or near the speed of the final product and at substantially higher frequencies than other available approaches by using our proprietary embedded synthesis technology that optimizes the final prototype performance. Certify achieves high performance for a multi-FPGA semiconductor prototype by optimizing all FPGAs in the prototype simultaneously.
The Certify product also includes schematic representations of several commercially available hardware prototyping systems to enable rapid prototype implementation without the need to create and build a custom prototyping platform. By partnering with leading hardware vendors via our “Partners in Prototyping” program, we accelerate prototype implementation and make FPGA-based prototyping accessible to customers who may otherwise be unwilling or unable to develop a custom hardware platform of their own.
While our Certify product serves the needs of ASIC designers verifying their design using multiple FPGAs, our Synplify Premier product is effective in verification situations which involve a single FPGA. Many ASIC verification teams use a single FPGA to verify a portion of their design. Our Synplify Premier product incorporates a number of features, also available in the Certify product, that facilitate the synthesis of an ASIC design into an FPGA. In addition, the Synplify Premier solution incorporates debug features found in our Identify product which improve the productivity associated with locating and fixing design problems.
Our products are designed to be utilized quickly and effectively by our customers and to minimize the level of support from us for the designer to be productive. Our customers use our products along with design software from semiconductor manufacturers and from other third party design software developers. The overall semiconductor design process is complex, and our customers may seek assistance from us with various aspects of our products’ functionality in their semiconductor design process. We believe that high quality customer support of our customers’ activities is important to the success of our business. We have developed a comprehensive support organization to manage customer accounts. We provide support for our products primarily from our Sunnyvale, California and Bangalore, India locations.
We provide technical support to our customers through maintenance services. Time-based licenses include maintenance services for the duration of their respective terms. For each sale of a perpetual or two or three-year term license, the first year of maintenance is generally sold with the license. Thereafter, customers may annually elect to renew maintenance. We price our maintenance service at or near the list price for maintenance, which is either 15% or 20% of the perpetual license list price, depending on the product.
Historically, approximately 80% of our outstanding maintenance contracts have been renewed each year. We believe this renewal rate will continue because the rate of innovation in the semiconductor industry, especially with FPGAs, is high and equipment manufacturers expect us to support the latest components as soon as they are available. Customers paying maintenance receive software updates for new components when and if we make these updates available. These frequent releases typically include support for new components and enable our customers to optimize their designs or create prototypes using those components. We work closely with leading FPGA manufacturers to incorporate support for new components as quickly as possible.
We generally provide our support via electronic mail, our web site and telephone. Our support organization may assist customers with technical support during the customers’ initial product installation and configuration. However, our support organization devotes the majority of its efforts to resolving customer questions about our products’ functionality that can arise from the customers’ design tasks. Effective execution of these efforts require highly skilled engineers familiar with our customers’ design tasks as well as familiarity with third party products that may be used by the customer in conjunction with our products. Our support staff consists of engineers with substantial design experience.
As of December 31, 2006, we had over 1,800 active customers. Of that total, 218 were first-time customers in 2006. Although in the past our customers were concentrated in the networking and communications industries, in 2006 our customers were more evenly distributed over networking and communications, semiconductor, military and aerospace, consumer, computer and peripheral, and other industries. Our customers often buy licenses for a single location, department or division, and then, based upon the initial success of the products, later expand their use of our products into other parts of their organizations. We believe we can sell our existing products more extensively within our existing customer base and sell them new products as we expand our product line. We will continue to pursue enterprise-wide sales as appropriate. We have customers throughout North America, principally the United States, as well as in Europe, Japan and other parts of Asia. See Note 10 of the consolidated financial statements for a full description of financial information about geographic areas. See also “Risk Factors” regarding the risks associated with our international operations. In 2006, 2005 and 2004, no customer comprised more than 10% of our revenue.
Marketing and Sales
We focus our marketing efforts on creating awareness for our products and generating leads for our sales organization. Our strategy is to distinguish our products by their high level of design performance, ease of use and time to market advantages. We employ a wide variety of communication channels to inform customers and potential customers about our products. These channels include our, or our key partners’, websites, print and web advertising, public relations, web-based seminars, live seminars, tradeshows and electronic mail notifications to customers about new product releases, as they become available.
We license our software products primarily through our direct sales organization, as well as distributors and other strategic partners.
Our direct sales efforts target customers who design semiconductors for networking and communications, semiconductor, military and aerospace, consumer, computer and peripheral , and other electronics systems. As of December 31, 2006, our direct sales staff consisted of 91 employees based in 12 offices around the world. Direct sales accounted for 90%, 91% and 88% of our total revenue in 2006, 2005 and 2004, respectively. Each of our sales teams represents a geographic region and includes a sales manager and applications engineer, and may also include an internal sales representative. The direct sales team also relies on strategic partners for demand creation and leads. Our typical sales cycle varies by product from two weeks to several months.
We currently have domestic direct sales offices in Sunnyvale, California; San Diego and Newport Beach, California; Denver, Colorado, Covington, Washington; Austin and Dallas, Texas; Lisle, Illinois; Durham, North Carolina; Bel Air, Maryland; Millersville, Maryland and Andover, Massachusetts. We also have international direct sales/marketing offices in or near Berkshire, Oxon, Hatfield, United Kingdom; Aix-en-Provence, France; Venray, The Netherlands; Dornach, Germany; Kista, Sweden; Netanya, Israel; Bangalore, India; Shanghai, P.R.C; Hsinchu City, Taiwan; Seoul, South Korea and Tokyo, Japan.
In addition to our direct sales strategy, we have indirect sales channels through distributors. Our relationships with distributors help extend our reach to more customers. Distributors either assist our direct sales staff or are our sole sales and support representatives in territories that include portions of Europe and Asia. Our international distributors typically perform marketing, sales and technical support functions in their respective country or region. We train our international distributors in both our products and sales methods. In general, each one may distribute directly to the customer, via other resellers or through a mixture of both channels. Our distributor agreements do not provide for rights of return, stock rotation or price protection for the distributor. Revenue from distribution was 2% of our total revenue in 2006, 2% of our total revenue in 2005 and 4% of our total revenue in 2004. We also generate some revenue through certain FPGA manufacturers as discussed below.
In the past we have experienced fluctuations in the sale of licenses for our products due to seasonality. For example, sales may decline during the summer months and we have experienced and anticipate we will continue to experience relatively lower product bookings in the first quarter of our fiscal year due to patterns in the capital budgeting and purchasing cycles of our current and prospective customers and the economic incentives for our sales force.
Our key strategic partners include certain semiconductor manufacturers and their distributors, and electronic design automation software companies, which provide information and interfacing that assist us with the successful development and distribution of our software solutions.
FPGA manufacturers . These partners work closely with us before each product release to ensure that our design software products perform optimally with their components. We rely on these manufacturers to provide us advance information and answer detailed questions about their components and design software. Partners currently include Achronix Semicondutor Corporation, Actel Corporation, Altera Corporation, and Lattice Semiconductor Corporation. Actel, Xilinx and Lattice also resell a version of our Synplify product. These reselling relationships provide a strong endorsement of our products, expand our sales channels and serve to introduce our products to a large number of potential customers. The reselling relationships generated 8% of our total revenue in 2006, 7% of our total revenue in 2005 and 8% of our total revenue in 2004.
Research and development
We believe that strong product development capabilities are essential to our strategy of enhancing our core technology, developing additional applications and increasing the competitiveness of our product offerings. We have invested significant time and resources in creating a structured process for undertaking all product development projects. This process involves key functional groups within our company and is designed to provide a framework for defining and addressing the steps required to bring product concepts and development projects to market successfully. Our product development strategy emphasizes rapid innovation and frequent and continued product releases. In 2006 we continued building our development teams in Bangalore, India and Ankara, Turkey as a way to lower our operating costs, while expanding our research and development organization. These two sites account for about 32% of the total research and development headcount.
We actively recruit key computer engineers and software developers with expertise and degrees in computer science, electrical engineering and other engineering disciplines. As of December 31, 2006, we had 151 employees engaged in research and development activities and related customer support services. Our research and development expenses were $23.4 million in 2006, $24.3 million in 2005 and $23.5 million in 2004.
Our software products rely on our internally developed intellectual property and other proprietary rights. We rely primarily on a combination of patent, copyright, trademark and trade secret laws, confidentiality procedures and contractual provisions to protect our intellectual property and other proprietary rights. We believe that these measures afford only limited protection. We have filed a number of patent applications and to date have been issued or allowed 42 patents that expire 20 years from their filing dates, the first of which expires in 2018. We license our software products primarily under shrink wrap licenses that are included as part of the product packaging. Shrink wrap licenses are not negotiated with or signed by individual customers, and purport to take effect upon the opening of the product package or use of the software license key. The legal enforceability of shrink wrap licenses is uncertain in many jurisdictions. We also enter into confidentiality agreements with our employees and technical consultants. Despite our efforts to protect our proprietary rights, unauthorized parties may attempt to copy aspects of our products or obtain and use information that we regard as proprietary. Policing unauthorized use of our products is difficult and we are unable to determine the extent to which piracy of our software products exists. In addition, the laws of some foreign countries do not protect our proprietary rights as fully as do the laws of the United States.
We are not aware that our products employ technologies that infringe any valid proprietary rights of third parties. We expect that software product developers will increasingly be subject to infringement claims as the number of products and competitors in our industry segment grows and the functionality of products in different industry segments overlaps. From time to time third parties have claimed that our products violate their proprietary rights but none of these claims has resulted in litigation or material expense. Any infringement claims, with or without merit, could:
be time-consuming to defend;
result in costly litigation or damage awards;
divert management’s attention and resources;
cause product shipment delays; or
require us to enter into royalty or licensing agreements.
These royalty or licensing agreements may not be available on terms acceptable to us, if at all.
Prabhu Goel has served as chairman of IPNI, a wholly-owned subsidiary of Tech Mahindra, an information technology services and solutions company, since February 2007. From October 1998 to January 2007, Dr. Goel served as chairman of iPolicy Networks, Inc., a network security products company, whose assets were acquired by Tech Mahindra in January 2007. From October 1998 to December 2004, Dr. Goel also served as chief executive officer of iPolicy. From April 2001 to June 2006, Dr. Goel served as chairman and chief executive officer of Tharas Systems, Inc., an electronic design automation company acquired in January 2007 by EVE, an electronic design automation company. Dr. Goel holds Masters of Science and Doctorate degrees in Electrical Engineering from Carnegie Mellon University.
Kenneth S. McElvain, one of Synplicity’s co-founders, has served as Synplicity’s chief technology officer, vice president and director since its inception. Mr. McElvain also served as president from 1994 to January 1996, and chief executive officer from January 1996 to July 1997. Mr. McElvain holds a Bachelor of Arts degree in Mathematics and a Bachelor of Science degree in Computer Science from Washington State University.
Gary Meyers has served as Synplicity’s president and chief executive officer since October 2004, and as president and chief operating officer between August 2004 and October 2004. Mr. Meyers became a director in January 2005. Mr. Meyers served as Synplicity’s vice president of worldwide sales from November 1999 to August 2004, vice president of north american sales from January 1999 to November 1999, and western area sales manager from January 1998 to January 1999. Mr. Meyers holds a Bachelor of Science degree in Electrical Engineering from the University of Maryland and a Masters of Business Administration degree from the University of California at Los Angeles.
Dennis Segers has served as chief executive officer of Tabula, Inc., a privately-held fabless semiconductor company since May 2006. From January 2006 to May 2006, Mr. Segers was an entrepreneur in residence at Benchmark Capital Partners, an early stage venture capital firm. From September 2001 to January 2006, Mr. Segers served as chief executive officer and president of Matrix Semiconductor, Inc., a fabless semiconductor company, and served on Matrix’s board of directors from February 1999 to January 2006, when Matrix was acquired by SanDisk Corporation. Mr. Segers holds a Bachelor of Science degree in Electrical Engineering from Texas A&M University.
Scott J. Stallard has served in various capacities at Hewlett-Packard Co. since 1975. Since May 2003, Mr. Stallard has served as Hewlett Packard’s senior vice president and general manager enterprise storage & servers in the Technology Systems Group. From May 2002 to May 2003, Mr. Stallard served as senior vice president, Business Critical Systems global business unit. From December 1999 to May 2002, Mr. Stallard served as vice president and general manager of Hewlett-Packard’s Business Systems and Technology Organization. Mr. Stallard holds a Bachelor of Science degree in Electrical Engineering and Computer Science from the University of California at Berkeley and a Masters of Science degree in Electrical and Computer Science from Stanford University.
Thomas Weatherford has been a consultant and private investor since January 2003. From 1997 to December 2002, Mr. Weatherford served as executive vice president and chief financial officer of Business Objects, S.A., a provider of business intelligence software. He currently serves on the boards of directors of Saba Software, Inc., a provider of human capital development and management solutions, Tesco Corporation, a global provider of technology-based solutions to the upstream energy industry, SMART Modular Technologies (WWH), Inc., an independent designer, manufacturer and supplier of value added systems to original equipment manufacturers, Advanced Analogic Technologies, Inc., a provider of power management semiconductor products for the communications, computing, and consumer portable and personal electronics and Mellanox Technologies, a supplier of semiconductor-based products that facilitate data transmission between servers, communications infrastructure equipment and storage systems. Mr. Weatherford holds a Bachelor of Business Administration degree from the University of Houston.
Alisa Yaffa, one of Synplicity’s co-founders, has served as chairwoman of the board of directors, vice president of intellectual property and secretary since March 1997, October 1998 and inception, respectively. Ms. Yaffa also served as Synplicity’s chief executive officer from inception to January 1996 and president from January 1996 to July 1997. From inception to October 1998, Ms. Yaffa served as Synplicity’s chief financial officer. Ms. Yaffa holds a Bachelor of Arts degree in Applied Mathematics and Computer Science from the University of California at Berkeley.
MANAGEMENT DISCUSSION FROM LATEST 10K
2006 Financial Overview
Total revenue for 2006 was $62.5 million, an 1% increase from $61.9 million in 2005
License revenue for 2006 was $17.9 million, an 8% decrease from $19.5 million in 2005
Maintenance revenue for 2006 was $27.2 million, a 7% increase from $25.4 million in 2005
Bundled license and services revenue for 2006 was $17.5 million, a 2% increase from $17.1 million in 2005
Operating income for 2006 was $1.5 million, which included stock-based compensation expense of $3.6 million. In 2005, operating income was $5.2 million, which included an insignificant stock-based compensation benefit.
Net income for 2006 was $3.2 million, a 52% decrease from $6.6 million in 2005
Diluted net income per share for 2006 was $0.11, a 52% decrease from $0.23 in 2005
Working capital for 2006 was $52.3 million, an 11% increase from $47.3 million in 2005
Deferred revenue for 2006 was $18.4 million, an 11% increase from $16.6 million in 2005
Critical Accounting Estimates
Our discussion and analysis of our financial condition and results of operations are based upon our consolidated financial statements, which have been prepared in accordance with accounting principles generally accepted in the United States. The preparation of these financial statements requires us to make estimates and judgments that affect the reported amounts of assets, liabilities, revenue, expenses and related disclosure of contingent assets and liabilities. We base our estimates on historical experience and on various other assumptions that are believed to be reasonable under the circumstances, and we evaluate these estimates on an on-going basis. Actual results may differ from these estimates under different assumptions or conditions.
We license our software products as perpetual licenses, term licenses and time-based licenses. In addition, we also generate revenue from custom software development services, through distributors and original equipment manufacturers (“OEMs”).
Revenue recognition criteria
In accordance with AICPA Statement of Position 98-9, Modification of SOP No. 97-2 with Respect to Certain Transactions , we recognize revenue based upon the residual method after all elements other than maintenance have been delivered and the conditions stated below have been met:
evidence of an arrangement is received from the customer;
delivery of the product and license key has occurred;
the fee is fixed or determinable; and
collection of the fee is probable.
We make judgments as to whether collection of the fee is probable based on the analysis provided by our credit review procedures. Revenue on arrangements to end-user customers that have met all of the revenue recognition criteria except probability of collection is recognized as collection becomes reasonably assured, which is generally as payments are received. Revenue from sales to distributors, who do not have a right to return, is considered to have met the probability of collection criterion when either we have received payment for the product or we assess that we have a substantial and sustained history of collections from the distributor. In the fourth quarter of 2006, we recorded an additional $161,000 of revenues from distributors that we deemed to have substantial and sustained history of collections.
Additionally, we assess whether the fee is fixed or determinable for sales with non-standard payment terms by evaluating our history of collections from these customers and/or their current financial standing.
License and maintenance offerings
License and maintenance revenue
We offer perpetual licenses for our products, whereby the customer receives the right to use the software license indefinitely. The first year of maintenance, which is renewable in subsequent years, is typically sold with the perpetual license.
We also offer two and three year term licenses for certain products, where the customer has rights to use the license for such periods. The first year of maintenance, which is renewable in subsequent years during the term of the agreement, is typically sold with term licenses.
Maintenance revenue from perpetual and term licenses allows customers under maintenance agreements to receive unspecified product updates, electronic, internet-based and telephone technical support throughout their maintenance period, which is typically one year. The majority of our customers renew their maintenance contracts annually, at or near the list price for maintenance, which is either 15% or 20% of the license list price, depending on the product, which establishes vendor specific objective evidence (“VSOE”) of the fair value of maintenance.
For larger value contracts entered into subsequent to March 31, 2006, we incorporated substantive contractual maintenance renewal rates into our agreements, at a consistent percentage of the net license fee paid, which establishes VSOE of fair value of maintenance for that class of arrangement per SOP 97-2. This methodology can be applied to arrangements of either perpetual or multi-year term licenses, where the first year’s maintenance is generally purchased with the term or perpetual licenses and the subsequent years are optional and can be purchased at the same percentage of the net license fee as the first year’s maintenance.
Perpetual license and term license revenue is recognized upon delivery of the product as License Revenue in the Consolidated Statements of Operations (“Statements of Operations”). Maintenance revenue from perpetual and term license sales is recognized on a straight-line basis over the maintenance period as Maintenance Revenue in the Statements of Operations.
Bundled license and services revenue
We also generate revenue from time-based licenses. Time-based licenses include maintenance services for the duration of their terms. Revenue from time-based licenses is recognized as Bundled License and Services Revenue in the Statements of Operations, on a straight-line basis over the period of the maintenance, as we do not have VSOE of the fair value of maintenance for time-based licenses since it is not priced or offered separately from the license.
In addition, we periodically sell perpetual and term licenses to OEMs for incorporation into their products and distribution to their customers. As part of these arrangements we have certain maintenance and support obligations to the OEMs. Since the maintenance associated with these types of arrangements is not sold separately, we do not have sufficient VSOE of fair value to allocate revenue among the elements. Thus, we recognize revenue from these arrangements on a straight-line basis over the maintenance period.
In 2006, we entered into arrangements with certain OEMs to slightly modify our existing products to work with the individual OEMs’ products. For the customization services, we have been able to make dependable estimates of progress towards completion. Since the maintenance and customized services associated with these types of arrangement are not typically sold separately, we do not have sufficient VSOE of fair value to allocate revenue among the elements. Thus, we recognize revenue from these arrangements on a straight-line basis over the longer period of either the maintenance or the customization services.
Prior to 2006, we entered into various custom software development agreements with semiconductor manufacturers to customize certain of our Structured ASIC products. This work typically involved significant modifications to our products under a statement of work negotiated with the customer. When time-based licenses were purchased as part of the agreement and delivery of the customized product had occurred, we recognized revenue from both the development and license fees on a straight-line basis over the period of the maintenance, as we did not have VSOE of the fair value of maintenance for time-based licenses. When licenses were not being purchased as part of the agreement, we recognized revenue from these development fees on a percentage of completion basis as determined by the relationship of the contract costs incurred to date and estimated total contract costs, which are regularly reviewed during the life of the contract. Revenue recognized from these development agreements represented less than 10% of total revenue for 2006, 2005 and 2004 and was recorded in Bundled License and Services Revenue in the Statement of Operations.
On occasion, we may sell time-based licenses and perpetual or term licenses combined within a single order. For these transactions, we generally recognize revenue from the entire transaction on a straight-line basis over the term of the longest period of maintenance, as generally we do not have VSOE of the fair value of maintenance for the time-based licenses.
Goodwill, Intangible Assets and Capitalized Software Costs
In accordance with Statement of Financial Accounting Standards No. 142, Goodwill and Other Intangible Assets (“SFAS 142”), goodwill is not amortized but is tested for impairment using a fair value approach. Goodwill is tested for impairment annually during the fourth quarter as well as whenever indicators of impairment exist. Our intangible assets are being amortized using the straight-line method over the estimated useful life of five years.
In accordance with the provisions of Statement of Financial Accounting Standards No. 144, Accounting for the Impairment or Disposal of Long-Lived Assets (“SFAS 144”), long-lived assets, including intangible assets and property and equipment, are reviewed for impairment whenever events or changes in circumstances indicate that their carrying amount may not be recoverable. Recoverability of a long lived asset other than goodwill is measured by comparison of its carrying amount to the expected future undiscounted cash flows that the asset is expected to generate. An impairment charge is recorded if the carrying amount of the asset exceeds the sum of the expected undiscounted cash flows. Any impairment to be recognized is measured by the amount by which the carrying amount of the asset exceeds its fair value. Fair value is determined based on discounted cash flows or appraised values, depending upon the nature of the assets. Significant management judgment is required in forecasting future operating results and cash flows and, should different conditions prevail or judgments be made, material write-downs of net intangible assets and/or goodwill could occur.
In accordance with the provisions of Statement of Financial Accounting Standards No. 86, Accounting for the Costs of Computer Software to Be Sold, Leased, or Otherwise Marketed (“SFAS 86”), at each balance sheet date, our unamortized capitalized software costs are compared to the net realizable value of that product. The amounts by which the unamortized capitalized costs exceed the net realizable value of that asset are written off. Due to our exit from the Structured ASIC and ASIC synthesis markets in March 2006, we wrote off capitalized software development costs related to our ASIC products during the three months ended March 31, 2006 in the amount of $295,000. The restructuring charges are discussed in further detail in the paragraph below.
In March 2006, one of our partners, LSI Logic, announced its decision to cease further development of its RapidChip semiconductor product which served the Structured ASIC markets. Our Amplify RapidChip software product was designed specifically and exclusively for LSI Logic’s RapidChip product. After this announcement, we evaluated the impact of LSI Logic’s decision and other factors and decided to exit the Structured ASIC and ASIC synthesis markets and to refocus our efforts on our core competencies in FPGA synthesis, DSP synthesis and ASIC verification product lines. As a result, we eliminated certain positions in engineering, sales and marketing and reassigned various employees, principally in engineering, from ASIC to other areas where we perceived we had positive growth opportunities. On March 24, 2006, our Board of Directors approved our restructuring plan, which was implemented under the provisions of Statement of Financial Accounting Standards No. 146, Accounting for Costs Associated with Exit or Disposal Activities (“SFAS 146”). This restructuring program included an 8% reduction in force primarily focused in our research and development department and a write-off of capitalized software development costs to their net realizable value.
Allowance for Doubtful Accounts
We maintain and update quarterly an allowance for doubtful accounts for estimated losses resulting from the failure of our customers to make required payments. The balance in the allowance account is comprised of a specific reserve for any particular receivable when collectibility is not probable and a provision for non-specific accounts based on a specified range of percentages derived from historical experience applied to the outstanding balance in each aged group. If after pursuing collection efforts on a specifically reserved receivable, payment is not expected, the receivable is deemed uncollectible and is written off. Such losses have not been material in any year, however, if the financial condition of our customers deteriorates, resulting in an impairment of their ability to make payments, additional allowances may be required. The table in Schedule II, Valuation and Qualifying
Accounts and Reserves of this annual report provides a roll forward of the changes in the allowance for doubtful accounts.
Valuation Allowance for Deferred Tax Assets
We evaluate the need for a valuation allowance for deferred tax assets in accordance with the requirements of Statement of Financial Accounting Standards No. 109 (“SFAS 109”) and such evaluations are based on available evidence of whether it is more likely than not that some portion or all of the deferred tax assets will not be realized. Our ability to generate positive domestic taxable income in 2007 is greatly dependent on the acceptance by our customers of new product introductions. Since the risks inherent in these new products is such that it limits our ability to generate verifiable forecasts of future domestic taxable income, a valuation allowance in an amount equal to our net deferred tax assets of December 31, 2006 was recorded.
Valuation of Stock Based Payments under SFAS 123R
Our stock option program is a broad-based, long-term retention program that is intended to attract and retain talented employees and align stockholder and employee interests. We primarily rely on two stock option plans that provide broad discretion to our Board of Directors to create appropriate equity incentives for members of our Board of Directors and our employees. Substantially all of our employees participate in our stock option program. On January 1, 2006, we adopted the provisions of SFAS 123R, requiring us to recognize expense related to the fair value of our stock-based compensation awards. We elected the modified prospective transition method as permitted by SFAS 123R. Under this transition method, stock-based compensation expense for the year ended December 31, 2006 includes compensation expense for all stock-based compensation awards granted prior to, but not yet vested as of December 31, 2005, based on the grant date fair value estimated in accordance with the original provisions of SFAS 123 and compensation expense for all stock-based compensation awards granted subsequent to December 31, 2005, based on the grant date fair value estimated in accordance with the provisions of SFAS 123R.
Determining the appropriate fair value model and calculating the fair value of share-based payment awards require the input of highly subjective assumptions, which represents management’s best estimate. A summary explanation follows:
Expected Stock Price Volatility —Our computation of expected volatility is based on historical volatility for the expected term of the options.
Expected Term of Option —Our expected term represents the period that our stock options are expected to be outstanding and was determined based on historical experience of similar stock options with consideration to the contractual terms of the stock options, vesting schedules and expectations of future employee behavior.
Expected Dividend Yield —The dividend yield assumption is based on our history and expectation of dividend payouts.
Expected Risk Free Interest Rate —The risk-free interest rate is based on the U.S. Treasury yield curve in effect at the time of grant for the expected term of the option.
Forfeiture Rate —The forfeiture rate is based on a review of recent forfeiture activity and expected future employee turnover.
See Note 1 to the consolidated financial statements for a further discussion on stock-based compensation.
Results of Operations
The following discussion compares our results of operations for 2006 with 2005 and 2005 with 2004. There is no assurance that our historical operating results are indicative of our future results.
In 2006, our total revenue grew by 1% over 2005. In 2006, license revenue decreased by 8%, maintenance revenue increased by 7% and bundled license and services revenue increased 2% over 2005. While we would expect total revenue to increase in 2007 compared to 2006, there are a number of factors that could negatively affect that outcome, including but not limited to the following:
performance of our sales force;
availability of new products and upgrades;
the acceptance of these new offerings to our customers;
economic health and markets of our customer base; and
in the case of maintenance, the decisions made by our customers to purchase or renew maintenance contracts.
We expect total revenue in 2007 to be between $65.0 million and $67.0 million.
In 2006, license revenue decreased 8% or $1.6 million from 2005. License revenue in 2006 was lower principally due to the decrease in ASIC orders caused by our exit from the Structured ASIC and ASIC synthesis markets in March 2006.
Revenue from the Structured ASIC and ASIC synthesis product line decreased 75% in 2006 compared to 2005, and contributed 1% to total license revenue. License revenue from the FPGA product line represented 89% of the license revenue and decreased 5% as we sold more bundled license and services revenue in 2006 compared to 2005. The ASIC verification product line revenue was flat with 2005, and was 7% of license revenue. The DSP product line license revenue increased 21% in 2006 from 2005, and was 3% of license revenue in 2006.
In 2005, license revenue increased 15% or $2.6 million over 2004. The FPGA product line revenue increased 13%, led by Synplify Pro and Synplify Premier, and represented 86% of total license revenue. ASIC verification product line license revenue in 2005 was substantially higher than in 2004, and represented 6% of license revenue. The DSP product line license revenue increased significantly in 2005 from 2004 on a percentage basis, however, it represented only 2% of total license revenue in 2005. License revenue from the Structured ASIC and ASIC synthesis product line decreased 9% in 2005 compared to 2004, and comprised 5% of license revenue in 2005.
Maintenance revenue. Maintenance revenue includes recognizable maintenance revenue from contracts associated with perpetual and term license sales.
In 2006, maintenance revenue increased 7% or $1.8 million over 2005. Revenue from the FPGA product line increased 7% in 2006 compared to 2005, and represented 91% of total maintenance revenue. The ASIC verification product line revenue increased 20% in 2006 from 2005, and comprised 5% of total maintenance revenue. The DSP product line maintenance revenue more than doubled on a percentage basis in 2006 over 2005, however, it represented only 1% of the total in 2006. Renewal rates remained constant in 2006 and 2005 and we realized an increase in customers returning to active maintenance in 2006 compared to 2005. As anticipated, maintenance revenue from the Structured ASIC and ASIC synthesis product line decreased 29% in 2006 compared to 2005, due to our exit from this market in the first quarter of 2006. The Structured ASIC and ASIC synthesis product line maintenance revenue was 3% of total maintenance revenue in 2006.
In 2005, maintenance revenue increased 11% or $2.5 million over 2004, led by an increase of 10% in the FPGA product line maintenance revenue which represented 91% of total maintenance revenue in 2005. The ASIC verification product line maintenance revenue increased 26% in 2005 over 2004, and was 5% of total maintenance revenue in 2005.
Bundled license and services revenue. Bundled license and services revenue includes revenue from time-based licenses which include and maintenance, development agreements, and other services such as consulting, technical support, and user guides.
In 2006, bundled license and services revenue increased 2% or $393,000. Revenue from the FPGA product line increased 16% in 2006 compared to 2005, and represented 40% of bundled license and services revenue in 2006. Revenue from the Structured ASIC and ASIC synthesis product line increased 7% in 2006 compared to 2005, and comprised 20% of bundled license and services revenue in 2006. The ASIC verification product line revenue decreased 16% in 2006 from 2005, and was 9% of bundled license and services revenue in 2006. The DSP product line revenue more than doubled on a percentage basis in 2006 from 2005, however, it contributed less than 1% of bundled license and services revenue in 2006. Custom software development services revenue decreased 9% in 2006 from 2005, due to our exit from the ASIC market and represented 31% of bundled license and services revenue in 2006.
In 2005, bundled license and services revenue decreased 1% or $142,000 from 2004. Revenue from the FPGA product line decreased 16% in 2005 compared to 2004, and represented 35% of bundled license and services revenue in 2005. Custom software development services revenue decreased 10% in 2005 from 2004, and was 35% of bundled license and services revenue in 2005. Revenue from the Structured ASIC and ASIC synthesis product line increased 42% in 2005 compared to 2004, and comprised 19% of bundled license and services revenue in 2005. The ASIC verification product line revenue increased 55% in 2005 from 2004, and was 11% of bundled license and services revenue in 2005.
Cost of revenue
Cost of license revenue. Cost of license revenue includes royalties, product packaging costs, software documentation, licensing costs including amortization of capitalized software development costs and other costs associated with shipping perpetual and term licenses.
Cost of license revenue increased 10% in 2006 from 2005 and 24% in 2005 from 2004 primarily due to amortization of purchased software that we incorporate into our products.
Cost of maintenance revenue. Cost of maintenance revenue consists of the costs of personnel, including stock-based compensation, and other expenses related to providing electronic, internet-based and phone technical support to our customers under active maintenance contracts who purchased perpetual and term licenses.
MANAGEMENT DISCUSSION FOR LATEST QUARTER
Results of Operations
The following discussion compares our results of operations for the three and nine months ended September 30, 2007 with the three and nine months ended September 30, 2006. There is no assurance that our historical operating results are indicative of our future results.
Three and Nine Months Ended September 30, 2007 and 2006
For the three months ended September 30, 2007, our total revenue increased 19% over the three months ended September 30, 2006. FPGA implementation revenue increased by 9%, ASIC verification revenue, which include revenue from the HAPS product line, increased by 44%, ESL revenue increased by 53% and ASIC revenue decreased, as expected, from $1.2 million in 2006 to $496,000 in 2007.
In the three months ended September 2007 license and systems revenue was 40% of total revenue, maintenance revenue was 37% of total revenue and bundled license and service revenue was 24%. In the three months ended September 2006 license and systems revenue was 31% of total revenue, maintenance revenue was 42% of total revenue and bundled license and service revenue was 26%. This mix will vary depending on the proportion of time-based licenses compared to total licenses booked, however, we anticipate that the sale of HAPS products will cause the license and systems revenue to increase relative to our other revenue sources.
For the nine months ended September 30, 2007 total revenue increased 11% from the nine months ended September 30, 2006. FPGA implementation revenue increased 5%, ASIC verification revenue increased 31%, ESL revenue increased 83% and ASIC revenue decreased, as expected, from $4.2 million in 2006 to $1.7 million in 2007.
In the nine months ended September 2007 license and systems revenue was 34% of total revenue, maintenance revenue was 40% of total revenue and bundled license and service revenue was 26%. In the nine months ended September 2006 license and systems revenue was 27% of total revenue, maintenance revenue was 44% of total revenue and bundled license and service revenue was 29% of total revenue.
License and systems revenue increased 51% from the three months ended September 30, 2006 over the three months ended September 30, 2007, driven principally by the sales of HAPS products. Perpetual and term license revenue from FPGA implementation increased 3%, ESL revenue increased 24%, ASIC verification revenue, including HAPS, increased 119% and, as expected, ASIC synthesis revenue declined by 55%.
For the nine months ended September 30, 2007, license and systems revenue increased by 38% over the nine months ended September 30, 2006. Perpetual and term license revenue from FPGA implementation was flat, ESL revenue increased 75%, ASIC verification revenue, including HAPS, increased 12% and, as expected, ASIC synthesis revenue declined by 17%.
Maintenance revenue. Maintenance revenue is derived from contracts associated with perpetual and term license sales. Our customers purchase the first year of maintenance with the perpetual or term license and a substantial number of them renew their maintenance in the years that follow. As a percentage of total revenue, maintenance revenue will vary depending on our mix of perpetual, term and time-based licenses as well as our cancellation rate.
In the three and nine months ended September 2007, maintenance revenue increased modestly over the comparable periods of 2006. While our renewal rate remained the same in all periods, the mix of applicable licenses generating maintenance revenue was more heavily weighted to time-based licenses which are booked in bundled license and services revenue. In all periods presented about 60% of our maintenance revenue is derived from FPGA implementation licenses and about 37% is derived from ASIC verification licenses. ASIC verification licenses include HAPS sales which do not carry a maintenance contract.
Bundled license and services revenue. Bundled license, systems and services revenue includes revenue from time-based licenses which include maintenance, development and OEM agreements, and revenue from other services such as consulting, technical support, and user guides.
In the three months ended September 2007, bundled license and services revenue increased by 9% over the same period in 2006. Higher OEM revenues offset the expected decrease in ASIC synthesis revenues. In the nine months ended September 2007, bundled license and services revenue was flat compared to the same period in 2006. A higher time-based license rate generated increases in FPGA implementation and ASIC verification software revenue, however, ASIC synthesis revenue was lower , as expected and OEM revenue was higher by 6%.
Cost of revenue
Cost of license and systems revenue. Cost of license and systems revenue includes the costs of systems sold (raw materials, contract manufacturing costs), royalties, product packaging costs, software documentation, licensing costs including amortization of capitalized software development costs and other costs associated with shipping licenses.
For the three months ended September 30, 2007, cost of license and systems revenue increased $934,000 from the three months ended September 30, 2006, due to the cost of sales associated with our HAPS systems sold.
For the nine months ended September 30, 2007, cost of license and systems revenue increased $1.3 million over the nine months ended September 30, 2006, principally due to the cost of sales associated with our HAPS systems sold.
Cost of maintenance revenue. Cost of maintenance revenue consists of the costs of personnel, including stock-based compensation, and other expenses related to providing electronic, internet-based and phone technical support to our customers under active maintenance contracts.
For the three months ended September 30, 2007, cost of maintenance revenue increased 10% from the three months ended September 30, 2006, principally due to higher stock-based compensation expense.
For the nine months ended September 30, 2007, cost of maintenance revenue decreased 3% from the nine months ended September 30, 2006, due to lower customer support expenses, offset by higher stock-based compensation expense.
Cost of bundled license and services revenue. Cost of bundled license and services revenue consists of engineering costs directly associated with our custom software development service contracts, and time-based licenses.
For the three months ended September 30, 2007, cost of bundled license and services revenue increased 48% from the three months ended September 30, 2006, due to an increase in development contracts.
For the nine months ended September 30, 2007, cost of bundled license and services revenue decreased 2% from the nine months ended September 30, 2006, as a result of a reduction in the time-based license rate, offset by increased costs associated with development work.
Amortization of intangible assets. Amortization of intangible assets reflects the amortization of intangible assets acquired as part of our purchases of products and technology from IOTA and Bridges2Silicon in 2002, as well as a purchase of technology for use in our products in 2006. In addition, amortization of intangible assets also reflects the amortization of intangible assets acquired as a result of the HARDI acquisition. Intangible assets are expensed over two to five-year useful lives.