Dailystocks.com - Ticker-based level links to all the information for the Stocks you own. Portal for Daytrading and Finance and Investing Web Sites
DailyStocks.com
What's New
Site Map
Help
FAQ
Log In
Home Quotes/Data/Chart Warren Buffett Fund Letters Ticker-based Links Education/Tips Insider Buying Index Quotes Forums Finance Site Directory
OTCBB Investors Daily Glossary News/Edtrl Company Overviews PowerRatings China Stocks Buy/Sell Indicators Company Profiles About Us
Nanotech List Videos Magic Formula Value Investing Daytrading/TA Analysis Activist Stocks Wi-fi List FOREX Quote ETF Quotes Commodities
Make DailyStocks Your Home Page AAII Ranked this System #1 Since 1998 Bookmark and Share


Welcome!
Welcome to the investing community at DailyStocks where we believe we have some of the most intelligent investors around. While we have had an online presence since 1997 as a portal, we are just beginning the forums section now. Our moderators are serious investors with MBA and CFAs with practical experience wwell-versed in fundamental, value, or technical investing. We look forward to your contribution to this community.

Recent Topics
Article by DailyStocks_admin    (10-27-08 03:33 AM)

The Daily Magic Formula Stock for 10/25/2008 is Cadence Design Systems Inc. According to the Magic Formula Investing Web Site, the ebit yield is 18% and the EBIT ROIC is 50-75 %.

Dailystocks.com only deals with facts, not biased journalism. What is a better way than to go to the SEC Filings? It's not exciting reading, but it makes you money. We cut and paste the important information from SEC filings for you to get started on your research on a specific company.


Dailystocks.com makes NO RECOMMENDATIONS whatsoever, and provides this for informational purpose only.

BUSINESS OVERVIEW

Overview

We develop electronic design automation, or EDA, software and hardware. We license software, sell or lease hardware technology and provide design, methodology and education services throughout the world to help manage and accelerate electronics product development processes. Our broad range of products and services are used by the world’s leading electronics companies to design and develop complex integrated circuits, or ICs, and electronics systems. We have approximately 5,300 employees, in approximately 60 sales offices, design centers and research and development facilities located around the world.

We were formed as a Delaware corporation in April 1987. Our headquarters is located at 2655 Seely Avenue, San Jose, California 95134. Our telephone number is (408) 943-1234. Our website can be accessed at www.cadence.com . We make available free of charge copies of our SEC filings and submissions on the investor relations page of our website at www.cadence.com as soon as practicable after electronically filing or furnishing such documents with the SEC. Our Corporate Governance Guidelines, Code of Business Conduct and the charters of the Audit Committee, Compensation Committee and Corporate Governance and Nominating Committee of our Board of Directors are also posted on the investor relations page of our website at www.cadence.com . Stockholders may also request copies of these documents by writing to our Corporate Secretary at the address above.

Factors Driving the Electronic Design Automation Industry

Communications, computing and consumer electronics markets drove the growth in the electronics industry for most of the past decade. However, in recent years, the consumer market has been the fastest growing end market for electronics and the most influential in setting requirements for time-to-market, low cost, miniaturization and increasing functionality. These market and technology forces pose major challenges for the global electronics design community.

During 2007, we saw increasing pressures on research and development budgets in our customer base, due to the deceleration of growth in the electronics equipment and semiconductor industries and a deteriorating macroeconomic environment. Semiconductor volumes grew during 2007, fueled by strong consumer demand in traditional and emerging markets, but at the same time average selling prices declined.

Electronic systems companies respond to demand for increased functionality and miniaturization by combining subsystems – such as radio frequency wireless communication, or RF, video signal processing, and microprocessors – onto a single silicon chip, creating a system-on-chip, or SoC, or multiple chips into a single chip package in a format referred to as system-in-package, or SiP. These trends toward subsystem integration have required chip makers to find solutions to challenges previously addressed by system companies, such as verifying system-level functionality and hardware-software interoperability.

SoC designs put many more transistors on each chip, increasing the need for tight control over power consumption. This is done not only to increase battery life in portable devices, but also to minimize energy cost for computing and networking equipment. Higher power devices generate more heat, which further increases both system cost as well as operating expenses for cooling. Evolving semiconductor manufacturing processes with smaller features (transistors and wires) and lower supply voltages address both of these issues to some degree, but introduce new challenges of their own. Contemporary portable electronic devices contain chips in which individual features can be as small as 45 nanometers – 45/1,000,000ths of a millimeter. Because of the electrical characteristics of the materials used to construct the transistors (which are essentially microscopic switches), chips continue to consume power even when transistors in the device are switched off. To overcome these and other power-related issues, specific “low power” design techniques must be developed and are most effective if they are integrated throughout the design flow, from logic design and verification through physical implementation.

Variability in the processes and materials used to manufacture silicon chips have become so pervasive at 65 nanometers and below that traditional connections between design and manufacturing teams are insufficient to ensure chip performance and yield. Integrating detailed models of the manufacturing process into the chip design environment is desirable so engineers can craft the design to avoid or overcome these manufacturing process variations. Similarly, manufacturing teams can optimize their processes if, along with the design, they are provided with information about the most critical parts of the chip. However, sharing information between design and manufacturing processes is complicated because current data formats used to describe the chip design differ from data formats used to describe the manufacturing process and control the manufacturing equipment. Moreover, design and manufacturing often take place within two or more separate companies, since multiple companies may participate in the design of the chip, and multiple companies may participate in the manufacturing and assembly of the final device.

These trends represent significant new challenges for electronics design processes. Specifically, product performance and size requirements of the mobile consumer electronics market require microelectronic systems to be smaller, consume less power and provide multiple functions all in one SoC or SiP package. This requires designers to pay close attention to many electrical, physical and manufacturing effects that were inconsequential in previous generations of chip designs. The design challenge becomes more complex with each new generation of electronics, and providers of EDA solutions must deliver products that address these technical challenges, while improving the efficiency and productivity of the design process.

Operating Segment

Our chief operating decision maker is our President and Chief Executive Officer, or CEO. Our CEO reviews our consolidated results within only one operating segment.

Products

Our products are engineered to improve our customers’ design productivity and resulting design quality by providing a comprehensive set of EDA design tools. Product revenues include all fees earned from granting licenses to use our software, and from sales and leases of our hardware products, and exclude revenues derived from maintenance and services. We offer customers three license types for our software: perpetual, term and subscription. See “Software Licensing Arrangements” below for additional discussion of our license types.

Product revenue was $1,104.0 million, or 68% of our total revenue, in 2007, $982.7 million, or 66% of our total revenue, in 2006 and $851.5 million, or 64% of our total revenue, in 2005.

Product Strategy

With the addition of emerging nanometer design considerations to the already burgeoning set of traditional design tasks, complex SoC or IC design can no longer be accomplished using a collection of discrete design tools. What previously consisted of sequential design activities must be merged and accomplished nearly simultaneously without time-consuming data translation steps. We combine our design technologies into “platforms” for four major

design activities: functional verification, digital IC design, custom IC design and system interconnect design. The four Cadence ® design platforms are Incisive ® functional verification, Encounter ® digital IC design, Virtuoso ® custom design and Allegro ® system interconnect design platforms. In addition, we augment these platform product offerings with a comprehensive set of design for manufacturing, or DFM, products that service both the digital and custom IC design flows. These four platforms, together with our DFM products, comprise our primary product lines.

In order to provide our customers with products that are optimized and scaled to their specific project requirements, we introduced three product tiers. The “L” tier provides competitive technology for mainstream design projects. The “XL” tier is differentiated for more complex and leading edge design projects. The “GXL” tier is highly differentiated to address the most complex and challenging design projects in the industry.

Incisive Functional Verification Platform

The Incisive functional verification platform enables our customers to employ enterprise-level verification process automation, including verification planning, management and process tracking, with coordination of all verification activities across teams of specialists and different execution platforms.

The Incisive platform is tailored for three customer segments:


• Logic design engineers using traditional hardware description languages and testing techniques;
• Logic design teams that are also responsible for verification and need more automation; and
• Multi-specialist enterprise teams comprised of logic design engineers, dedicated verification engineers, software development engineers and system validation engineers.

The Incisive platform includes verification process automation technologies, methodologies, and verification intellectual property, or VIP, for many standard protocols. The Incisive platform is comprised of the following core solutions:


• The Incisive Management solution, which automates and guides the verification process and then analyzes data, from planning to closure;
• The Incisive Simulation Analysis solution, which offers mixed-language testbench support, dynamic assertion checking, transaction-level support, hardware description language, or HDL, analysis and a complete debug environment;
• The Incisive Formal solution, which improves productivity starting at the designer’s desktop, providing a formal means of verifying register transfer level, or RTL, functional correctness with assertions, without the need of testbench simulation, resulting in fast RTL block bring-up;
• The Incisive Verification IP, which improves productivity while reducing project risks associated with standard protocol compliance, providing a catalogue of the most popular standard protocols equipped with a Compliance Management System; and
• The Palladium ® and Xtreme ® series of emulation and acceleration hardware solutions, which accelerate the verification process and enable first working silicon with first working software.

The Incisive Plan-to-Closure methodology and the SoC Functional Verification Kit are designed to enable the scalable deployment of best practices by our technical field experts and to mitigate our customers’ language, technology and methodology adoption risks.

Encounter Digital IC Design Platform

The Encounter digital IC design platform enables our customers to implement all aspects of their digital nanometer-scale designs. It is based on a single user interface and unified in-memory data model, and is specifically designed to facilitate the analysis and optimization of chip performance, power consumption, and silicon area and manufacturability throughout our customers’ design processes. The Encounter platform is comprised of the following core technologies:


• Silicon virtual prototyping for enabling designers to plan the complete implementation of a chip before committing to a specific design strategy;
• Global RTL and physical synthesis for creating and physically locating logic on the chip, while simultaneously optimizing performance, power, cost and yield;

• Signal integrity and yield-aware routing for connecting high performance physical interconnect between the logic gates;
• Signal integrity and nanometer delay analysis;
• Comprehensive design-for-test capability as well as post-silicon test diagnostics; and
• Logic equivalence checking and design constraint management capability for designers to verify that their RTL specification is equivalent to the final IC layout.

Unlike traditional “front-end/back-end” systems, the Encounter platform does not require customers to perform time-consuming translations between common tasks such as placement, power distribution, routing, and timing and crosstalk analysis. The Encounter platform supports hierarchical designs, with support for designs containing hundreds of millions of transistors on a single chip. Since 2005, the Encounter platform has been marketed in three tiers: Encounter L, XL and GXL. These tiers are scaled to provide customers with technologies tailored to specific degrees of design complexity in the digital IC space.

Virtuoso Custom Design Platform

The Virtuoso custom design platform provides designers with an integrated solution for design creation, validation and implementation of silicon-accurate analog, custom digital, mixed-signal and RF designs, while ensuring that these designs are ready for manufacturing, through our integrated DFM capabilities.

The Virtuoso platform reduces design time by providing:


• Reference flows for analog, mixed-signal, RF and analog-digital integration focused at the wireless and analog/mixed-signal markets;
• Automatic analog circuit sizing and optimization (including yield optimization);
• Multi-mode simulation (digital, analog, mixed-signal and RF) using a common syntax and model, and common equations;
• Fast custom layout technologies;
• Process migration technology;
• Electrical vs. physical effects analysis; and
• Physical design integration and silicon analysis for complex custom, cell-based and mixed custom designs.

The latest Virtuoso 6.1.0 release provides a unified design environment tying together the design, layout, and verification tasks based on innovative constraint-driven design capabilities, which significantly improve our customers’ productivity. The end-to-end simulation and verification technology called “multi-mode simulation” is integrated into the unified environment enabling a complete design-to-verification methodology.

The Virtuoso 6.1.0 platform relies on the OpenAccess tm database (described below in “Third Party Programs and Initiatives”), which provides a common foundation for the designers as they move through the design cycle and is also a mechanism to interoperate with applications developed by partners and customers.

The Virtuoso L, XL and GXL offerings provide designers the ability to choose the right products to match their needs for custom design ranging from the simplest entry-level component design to the most complex DFM-aware SoC designs.

Allegro System Interconnect Design Platform

The Allegro system interconnect design platform enables design teams to design high-performance electronic products across the domains of IC, package and printed circuit board, or PCB, reducing cost and time to market. The system interconnect – between input-output buffers and across ICs, packages and PCBs – can be optimized through the platform’s co-design methodology, reducing both hardware costs and design cycles. Designers use the Allegro platform’s constraint-driven methodology and advanced capabilities for design capture, signal integrity and physical implementation. Silicon design-in kits speed time to market by allowing IC companies to shorten new device adoption time and allowing systems companies to accelerate PCB system design cycles. In 2007, we shipped our next generation PCB design products that include our new global route environment technology as part of the Allegro 16.0 release. We also expanded sales of our IC Packaging and SiP products. The Allegro family products are marketed in three product tiers: Allegro L, XL and GXL.

The system interconnect design product group includes the Allegro system interconnect design platform, the OrCAD ® product line of PCB design products which are engineered for individual or small design team productivity and a family of IC packaging and SiP technologies. The OrCAD product line is marketed worldwide through a network of resellers.

Design for Manufacturing

With the advent of finer geometries in silicon manufacturing technologies (65 nanometer, 45 nanometer and below), semiconductor companies are increasingly concerned about manufacturability of their designs. The physical layout of each IC requires detailed analysis and optimization to ensure that the design can be manufactured in volume while performing as expected.

Cadence’s strategy is to integrate silicon foundry-endorsed model-based manufacturability analysis and sign-off into the proven IC design implementation flows from both the Virtuoso as well as the Encounter platforms. The benefits of this integrated manufacturability design flow include reduction of catastrophic and parametric yield issues and enablement of design implementation for maximized performance.

Some of our products that deliver DFM capabilities for nanometer SoC design include:


• QRC, Fire & Ice ® QX and Assura ® RCX parasitic extraction products, which take the designer’s physical representation of an IC and extract the electrical properties of that design representation to enable further analyses, such as simulation and timing analysis;
• Products in the VoltageStorm ® family analyze on-chip power distribution for digital, analog and SoC designs. VoltageStorm detects unanticipated voltage drop, enabling the customer to correct fatal conditions, thereby preventing extensive troubleshooting and delay during initial manufacturing;
• Our physical verification products, including Cadence Physical Verification System, or PVS, Assura, Diva ® and Dracula ® , which perform manufacturing design rule checks to ensure the proposed design meets the requirements of the foundry’s manufacturing process rules;
• Mask data preparation tools, such as MaskCompose and QuickView, which help customer mask shops create mask and reticle layouts for chips being manufactured in nanometer processes;
• Cadence CMP Predictor, which helps designers to understand the impact of chemical-mechanical polishing, or CMP, one of the major steps in the semiconductor manufacturing process, which potentially impacts the chip performance at advanced silicon geometries;
• Litho Physical Analyzer and Litho Electrical Analyzer, both lithography analysis tools for physical and electrical effects, which offer silicon foundry endorsed model-based layout printability and electrical variation analysis tools;
• Advanced pattern synthesis tools for next generation optical and process proximity correction of layouts targeted for finer geometries, especially extremely dense layouts such as full chip memory designs; and
• Other products for random yield analysis as well as chip failure diagnostics.

Kits

Today’s growing silicon complexity creates an array of design challenges for semiconductor and systems design teams. Among these challenges is the application of EDA technologies to overcome design hurdles in certain key markets driving the semiconductor industry, such as the wireless and networking segments. Cadence kits are designed to allow companies in these sectors to achieve shorter, more predictable design cycles and greater design productivity by greatly simplifying the application and integration of EDA technologies to address major design challenges in the analog mixed-signal, RF, SiP, low power and SoC functional verification markets.

A Cadence kit assembles technologies from our broad portfolio into ready-to-use design flows, enhanced by application specific design methodologies, expert knowledge, and best practices, and applied to a segment representative IC design. The kits accelerate the adoption of latest design methodologies and offer customers improved productivity. In 2007, we introduced the Low Power Kit and the SoC Functional Verification Kit.

Verification and Application-Specific Programming Services

We offer verification and application-specific programming, or ASP, services, which provide customers with consulting services, project services and/or complete turnkey services for verification acceleration and system emulation. QuickCycles allows customers access to our Palladium simulation acceleration and emulation products either on the customer internet site or remotely over a high-speed, secure network connection.

Third Party Programs and Initiatives

We recognize that certain of our customers may also use internally-developed design tools or design tools provided by other EDA companies, as well as IP available from multiple suppliers. We support the integration of third party design products through participation in the OpenAccess Initiative, the Connections ® and OpenChoice IP programs. OpenAccess is a full-featured EDA database that supports access and manipulation of its internal EDA data via a fully documented and freely available programming interface. This provides an open application program interface through which applications developed by our customers, by their other EDA vendors, or by university research groups can all operate within a single database and with our products. We have licensed the OpenAccess database to the OpenAccess Coalition, which is operated by the Silicon Integration Initiative, or Si2, an organization of EDA, electronic system and semiconductor industry leaders focused on improving productivity and reducing cost in creating and producing integrated silicon systems.

The Connections Program provides member companies with access to our products to ensure that our products work well with third party tools. The OpenChoice IP program was instituted to enable interoperability and facilitate open collaboration with leading providers of library, processor, memory core and verification IP to build, validate and deliver accurate models optimized for Cadence design and verification solutions. The program aims to ensure IP quality and provide our customers with access to a broad IP portfolio that works with our products. A key component of the OpenChoice program is to assist and support library providers in the integration of our design and verification products and model formats into customer-owned tooling, or COT, library solutions.

In 2007, the Power Forward Initiative membership grew to 24 electronics industry leaders who recognized the urgent need for an automated, power-aware design infrastructure to facilitate the production of ICs that consume significantly less power. This group participated in the refinement and standardization of the Common Power Format, or CPF. CPF is a specification language that holistically captures low-power design intent so that it can be communicated consistently throughout the IC design process. We have contributed the CPF specification to Si2, which manages the standardization, maintenance and distribution of CPF for the benefit of the electronics industry.

In addition, we work with vendors of Application-Specific Integrated Circuits, or ASICs, to ensure predictable and smooth handoff of design data from mutual customers to ASIC implementation. These programs foster relationships throughout the silicon design chain with leading IP partners, silicon manufacturers and library provider partners to support both ASIC and COT solutions for our customers. They are integral to providing complete design chain solutions to IC and electronic systems designers who depend on coordinated offerings from multiple suppliers.

Maintenance

We provide technical support to our customers to facilitate their use of our software and hardware products. A high level of customer service and support is critical to the adoption and successful use of our products. We have a global customer support organization and specialized field application engineering teams located in each of our operating regions to provide assistance to customers where and when they need it.

Standard maintenance support includes three major components: our Sourcelink ® online support portal, which provides 24 hour access to real-time technical information on our products; contact center support (telephone, email and web access to our support engineers); and software updates (periodic updates with regression-tested critical fixes and updated functionality available via CDs or secure internet download).

Maintenance is offered to customers as an integral, non-cancelable component of our subscription license agreements, or as a separate agreement subject to annual renewal for our term and perpetual license customers.

Some of our customers have relocated, or expanded the presence of their design teams, away from their headquarters or historical locations to locations in emerging growth regions. Accordingly, to provide responsive and effective support for these customers, we expect to continue expanding the presence of our own support and application engineering teams in these emerging growth regions.

Maintenance revenue was $385.2 million, or 24% of our total revenue, in 2007, $366.3 million, or 25% of our total revenue, in 2006 and $351.5 million, or 26% of our total revenue, in 2005. We expect that maintenance revenue in 2008 will be generated predominantly from backlog.

Services

We offer a number of fee-based services, including engineering and education services related to IC design and methodology. These services may be sold separately or sold and performed in conjunction with the sale, lease or license of our products.

Services revenue was $125.8 million, or 8% of our total revenue, in 2007, $134.9 million, or 9% of our total revenue, in 2006 and $126.2 million, or 9% of our total revenue, in 2005.

Engineering Services

We offer engineering services and reusable design technologies to aid customers with the design of complex ICs and the implementation of design capabilities. We focus our offerings primarily on SoC devices, including both ASICs and Application-Specific Standard Parts, and on analog and mixed-signal ICs. The customers for these services primarily consist of semiconductor and systems companies developing products for the communications, computing and consumer markets. We offer engineering capabilities to assist customers from product concept through volume manufacturing.

We also make our design IP portfolio available to customers as part of our technology and services solutions. These reusable design and methodology components enable us to more efficiently deliver our services, and allow our customers to reduce the design complexity and time to market for the development of complex SoCs.

In our design and methodology service practices, we leverage our cumulative experience and knowledge of design techniques and leading practices with many customers and different design environments to improve our own service teams’ and our customers’ productivity. We work with customers using outsourcing, consultative and collaborative models depending on their projects and needs. Our Virtual Computer-Aided Design, or VCAD, model enables our engineering teams at one or more of our locations to virtually work “side-by-side” with our customers’ teams located elsewhere during the course of their design and engineering projects through a secure private network infrastructure.

Through collaboration with our customers, we are able to design advanced ICs and gain direct and early visibility to industry design issues that may not be addressed adequately by today’s EDA technologies. This enables us to accelerate the development of new software technology and products to meet the market’s current and future design requirements.

Education Services

Our education services offerings include internet, classroom and custom courses, the content of which ranges from how to use the most recent features of our EDA products to instruction in the latest IC design techniques. The primary focus of education services is to accelerate our customers’ path to productivity in the use of Cadence products and increase awareness of the total solution required for engineering success.

Marketing and Sales

We generally use a direct sales force consisting of sales people and applications engineers to market our products and provide maintenance and services to existing and prospective customers. Applications engineers provide technical pre-sales and post-sales support for software products. Due to the complexity of many of our EDA products and the electronic design process in general, the sales cycle is generally long, requiring three to six months or more. During the sales cycle, our direct sales force generally provides technical presentations, product demonstrations and support for on-site customer evaluation of our software. We also use traditional marketing approaches to promote our products and services, including advertising, direct mail, telemarketing, trade shows, public relations and the internet. As EDA products mature and become widely understood by the marketplace, we selectively utilize value added resellers to broaden our reach and reduce cost of sales. All OrCAD and selected Incisive products are primarily marketed through these channels. With respect to international sales, we generally market and support our products and services through our subsidiaries.

Software Licensing Arrangements

We sell software using three license types: subscription, term and perpetual. Customers who prefer to license technology for a specified, limited period of time will choose either a subscription or term license, and customers who prefer to have the right to use the technology continuously without time restriction will choose a perpetual license. Customers who desire rights to remix in new technology during the life of the contract will select a subscription license, which allows them limited access to unspecified new technology on a when-and-if-available basis, as opposed to a term or perpetual license which does not include remix rights to new technology. Payment terms for subscription and term licenses generally provide for payments to be made in installments over the license period and payment terms for perpetual licenses generally are net 30 days.

Our revenue recognition depends on a number of contract-specific terms and conditions, including the license type, payment terms, creditworthiness of the customer and other factors as more fully described in this Annual Report under the heading “Critical Accounting Estimates” under Item 7, “Management’s Discussion and Analysis of Financial Condition and Results of Operations.” Revenue associated with subscription licenses is recognized over multiple periods during the license term, whereas product revenue associated with term and perpetual licenses is generally recognized upon the later of the effective date of the license or delivery of the product, assuming all other criteria for revenue recognition have been met. The amount of product revenue recognized from backlog varies from quarter to quarter. For the past three years the amount of product revenue recognized from backlog generally has been approximately two-thirds of total product revenue.

Our revenue and results of operations may miss expectations due to a shortfall in product revenue generated from current transactions or variance in the actual mix of license types executed in any given period, and due to other contract-specific terms and conditions as discussed above. We are subject to greater credit risk on subscription and term licenses, as compared to perpetual licenses, due to the installment payment terms generally associated with those license types. Otherwise, the particular risks of one license type versus another type do not vary considerably.

From time to time we sell receivables generated by our licenses with installment payment terms to third party financing institutions on a non-recourse or limited-recourse basis.

For a further description of our license agreements, revenue recognition policies and results of operations, please refer to the discussion under the heading “Critical Accounting Estimates” under Item 7, “Management’s Discussion and Analysis of Financial Condition and Results of Operations.”

Research and Development

Our investment in research and development was $494.0 million in 2007, $460.1 million in 2006 and $390.7 million in 2005.

The primary areas of our research and development include SoC design, the design of silicon devices in the nanometer range, high-performance IC packaging, SiP and PCB design, system-level modeling and verification, high-performance logic verification technology and hardware/software co-verification. Because the electronics industry combines rapid innovation with rapidly increasing design and manufacturing complexity, we make significant investments in enhancing our current products, as well as creating new products and technologies and integrating those products and technologies together into segmented solutions.

Our future performance depends largely on our ability to maintain and enhance our current product development and commercialization, to develop, acquire or operate with new products from third parties, and to develop solutions that meet increasingly demanding productivity, quality, predictability and cost requirements. In addition to our product development team, which focuses on new and existing products, we maintain Cadence Laboratories, an advanced research group responsible for exploring new technologies, moving those technologies into product development and maintaining strong industry relationships.

CEO BACKGROUND

Michael J. Fister
53 Years Old
Director Since 2004
President and Chief Executive Officer, Cadence Design Systems, Inc.
Michael J. Fister has served as President and Chief Executive Officer of Cadence since May 2004. Prior to joining Cadence, Mr. Fister spent 17 years at Intel Corporation, where he was most recently Senior Vice President and General Manager of the company’s Enterprise Platforms Group. Mr. Fister is a graduate of the University of Cincinnati where he received B.S. and M.S. degrees in electrical engineering. Mr. Fister also serves as a director of Autodesk, Inc.

Donald L. Lucas
78 Years Old
Director Since 1988
Private venture capital investor
Donald L. Lucas served as Chairman of the Board of Cadence from 1988 until May 2004. From its inception in 1983 until 1987, Mr. Lucas served as Chairman of the Board and a director of SDA Systems, Inc., a predecessor of Cadence. Mr. Lucas has been a private venture capital investor since 1960. Mr. Lucas also serves as a director of 51 job, Inc., DexCom, Inc., Oracle Corporation, Spansion, Inc. and Vimicro International Corporation.

Dr. Alberto Sangiovanni-Vincentelli
60 Years Old
Director Since 1992
Professor of Electrical Engineering and Computer Sciences, University of California, Berkeley
Dr. Alberto Sangiovanni-Vincentelli serves as a consultant to Cadence, providing services as Chief Technology Advisor, and has served as a consultant to Cadence, or one of its predecessor corporations, since 1983. Dr. Sangiovanni-Vincentelli was a co-founder of SDA Systems, Inc., a predecessor of Cadence. Dr. Sangiovanni-Vincentelli has been a Professor of Electrical Engineering and Computer Sciences at the University of California, Berkeley since 1976, where he holds The Edgar L. & Harold H. Buttner Chair of Electrical Engineering. In 1998, Dr. Sangiovanni-Vincentelli was elected to the National Academy of Engineering and, in 2001, was honored by the Electronic Design Automation Consortium with the Kaufman Award, honoring an individual who has contributed to creating or driving technological advances that have had measurable impact on the productivity of design engineers.

George M. Scalise
74 Years Old
Director Since 1989
President, Semiconductor Industry Association
George M. Scalise has served as President of the Semiconductor Industry Association, an association of semiconductor manufacturers and suppliers, since June 1997. Mr. Scalise served on the Board of Directors of the Federal Reserve Bank of San Francisco from January 2000 until December 2005, including as Deputy Chairman from January 2001 until March 2003 and as Chairman from March 2003 until December 2005. Mr. Scalise served as Executive Vice President and Chief Administrative Officer of Apple Computer, Inc. from March 1996 to May 1997. Mr. Scalise also served as Senior Vice President of Planning and Development and Chief Administrative Officer of National Semiconductor Corporation from 1991 to 1996. Mr. Scalise currently serves on President George W. Bush’s Council of Advisors on Science and Technology.


Dr. John B. Shoven
60 Years Old
Director Since 1992
Professor of Economics, Stanford University
Dr. John B. Shoven has served as Chairman of the Board since July 2005. Dr. Shoven is currently the Charles R. Schwab Professor of Economics at Stanford University, where he has taught since 1973. Dr. Shoven has served as director of the Stanford Institute for Economics Policy Research since November 1999 and served in that capacity from 1989 to 1993. Dr. Shoven served as Chairman of the Economics Department at Stanford University from 1986 to 1989 and as Dean of the School of Humanities and Sciences from 1993 to 1998. Dr. Shoven also serves as a director of Exponent, Inc., and a member of the Mountain View Board of American Century Funds. Dr. Shoven is also a member of the American Academy of Arts and Sciences.

Roger S. Siboni
53 Years Old
Director Since 1999
Independent Investor
Roger S. Siboni served as Chairman of the Board of Epiphany, Inc., a software company that provided customer relationship management solutions, from July 2003 until October 2005 and as President and Chief Executive Officer of Epiphany, Inc. from August 1998 to July 2003. Prior to joining Epiphany, Mr. Siboni spent more than 20 years at KPMG LLP, most recently as its Deputy Chairman and Chief Operating Officer. Mr. Siboni also serves as a director of Dolby Laboratories, Inc.

John A.C. Swainson
53 Years Old
Director Since 2006
Chief Executive Officer, CA, Inc.
John A.C. Swainson has served as the President and Chief Executive Officer of CA, Inc. since February 2005 and as President and Director since November 2004. Prior to joining CA, Mr. Swainson was Vice President of Worldwide Sales of IBM Corporation’s Software Group from July 2004 to November 2004 and General Manager of the Application Integration and Middleware division of IBM’s Software Group from 1997 to July 2004. Mr. Swainson also serves as a director of CA, Inc. and Visa Inc.

Lip-Bu Tan
48 Years Old
Director Since 2004
Chairman, Walden International
Lip-Bu Tan is the founder and Chairman of Walden International, an international venture capital firm founded in 1987. Mr. Tan also serves as a director of Creative Technology Ltd., Flextronics International Ltd., Semiconductor Manufacturing International Corporation and SINA Corporation. Mr. Tan received an M.S. in nuclear engineering from the Massachusetts Institute of Technology, an MBA from the University of San Francisco, and a B.S. from Nanyang University in Singapore.

MANAGEMENT DISCUSSION FROM LATEST 10K

Overview

We develop electronic design automation, or EDA, software and hardware. We license software, sell or lease hardware technology, provide maintenance for our software and hardware and provide design, methodology and education services throughout the world to help manage and accelerate electronics product development processes. Our broad range of products and services are used by the world’s leading electronics companies to design and develop complex integrated circuits, or ICs, and electronics systems.

With the addition of emerging nanometer design considerations to the already burgeoning set of traditional design tasks, complex SoC or IC design can no longer be accomplished using a collection of discrete design tools. What previously consisted of sequential design activities must be merged and accomplished nearly simultaneously without time-consuming data translation steps. We combine our design technologies into “platforms” addressing four major design activities: functional verification, digital IC design, custom IC design and system interconnect design. The four Cadence design platforms are Incisive functional verification, Encounter digital IC design, Virtuoso custom design and Allegro system interconnect design platforms. In addition, we augment these platform product offerings with a comprehensive set of DFM products that service both the digital and custom IC design flows. These four platforms, together with our DFM products, comprise our primary product lines.

Digital implementation was the fastest growing product group in 2007 in terms of revenue, driven by the focus on complex chips, advanced nodes and low power. Design challenges at the 65 nanometer and 45 nanometer process nodes drove upgrades in the digital, custom and DFM product groups. Also during 2007, the Allegro system interconnect design platform had a complete technology update and the custom simulation business had a significant product update.

We have identified certain items that management uses as performance indicators to manage our business, including revenue, certain elements of operating expenses and cash flow from operations, and we describe these items more fully below under the heading “Results of Operations” below.

Critical Accounting Estimates

In preparing our Consolidated Financial Statements, we make assumptions, judgments and estimates that can have a significant impact on our revenue, operating income and net income, as well as on the value of certain assets and liabilities on our Consolidated Balance Sheets. We base our assumptions, judgments and estimates on historical experience and various other factors that we believe to be reasonable under the circumstances. Actual results could differ materially from these estimates under different assumptions or conditions. At least quarterly, we evaluate our assumptions, judgments and estimates and make changes accordingly. We believe that the assumptions, judgments and estimates involved in the accounting for revenue recognition, accounting for income taxes and valuation of stock-based awards have the greatest potential impact on our Consolidated Financial Statements; therefore, we consider these to be our critical accounting estimates. Historically, our assumptions, judgments and estimates relative to our critical accounting estimates have not differed materially from actual results. For further information on our significant accounting policies, see Note 2 to our Consolidated Financial Statements.

Revenue recognition

We apply the provisions of Statement of Position, or SOP, 97-2, “Software Revenue Recognition,” as amended by SOP 98-9, “Modification of SOP 97-2, Software Revenue Recognition, With Respect to Certain Transactions,” to all software licensing transactions and to all product revenue transactions where the software is not incidental. We also apply the provisions of SFAS No. 13, “Accounting for Leases,” to all hardware lease transactions. We recognize revenue when persuasive evidence of an arrangement exists, the product has been delivered, the fee is fixed or determinable, collection of the resulting receivable is probable, and vendor-specific objective evidence of fair value, or VSOE, exists.

We license software using three different license types:


• Subscription licenses;
• Term licenses; and
• Perpetual licenses.

For many of our term and subscription license arrangements, we use our proprietary internet-based delivery mechanism, “eDA-on-tap,” to facilitate the delivery of our software products. To maximize the efficiency of this

delivery mechanism, we created what we refer to as “eDA Cards,” of which there are two types. Subscription license customers may purchase what we refer to as an “eDA Platinum Card,” which provides the customer access to and use of all software products delivered at the outset of the arrangement and the ability to use additional unspecified software products that may become commercially available during the term of the arrangement. Term license customers may purchase what we refer to as an “eDA Gold Card,” which provides the customer access to and use of all software products delivered at the outset of the arrangement. Overall, the eDA Cards provide greater flexibility for our customers in how and when they deploy and use our software products.

Subscription licenses – Our subscription license arrangements offer our customers the right to:


• Access and use all software products delivered at the outset of an arrangement throughout the entire term of the arrangement, generally two to four years, with no rights to return;
• Use unspecified additional software products that become commercially available during the term of the arrangement; and
• Remix among the software products delivered at the outset of the arrangement, as well as the right to remix into other unspecified additional software products that may become available during the term of the arrangement, so long as the cumulative value of all products in use does not exceed the total license fee determined at the outset of the arrangement. These remix rights may be exercisable multiple times during the term of the arrangement. The right to remix all software products delivered pursuant to the license agreement is not considered an exchange or return of software because all software products have been delivered and the customer has the continuing right to use them.

Customers that purchase an eDA Platinum Card have the ability during the term of the arrangement to use software products delivered at the outset of the arrangement, and to use other unspecified additional software products that may become commercially available during the term of the arrangement, until the fees have been depleted.

In general, revenue associated with subscription licenses is recognized ratably over the term of the license commencing upon the later of the effective date of the arrangement or delivery of the software product. Subscription license revenue is allocated to product and maintenance revenue. The allocation to maintenance revenue is based on vendor specific objective evidence, or VSOE, of fair value of the undelivered maintenance that was established in connection with the sale of our term licenses.

In the event that a subscription license arrangement is terminated by mutual agreement and a new term license arrangement is entered into either concurrently with or subsequent to the termination of the subscription license arrangement, the revenue associated with the new term license arrangement is recognized upon the later of the effective date of the arrangement or delivery of the software product, assuming all other criteria in SOP 97-2 have been met.

Term licenses – Our term license arrangements offer our customers the right to:


• Access and use all software products delivered at the outset of an arrangement throughout the entire term of the arrangement, generally two to four years, with no rights to return; and
• Remix among the software products delivered at the outset of the arrangement, so long as the cumulative value of all products in use does not exceed the total license fee determined at the outset of the arrangement. These remix rights may be exercisable multiple times during the term of the arrangement. The right to remix all software products delivered pursuant to the license agreement is not considered an exchange or return of software because all software products have been delivered and the customer has the continuing right to use them.

Customers that purchase an eDA Gold Card have the ability during the term of the arrangement to use software products delivered at the outset of the arrangement until the fees relating to the arrangement have been depleted.

In general, revenue associated with term licenses is recognized upon the later of the effective date of the arrangement or delivery of the software product.

Perpetual licenses – Our perpetual licenses consist of software licensed on a perpetual basis with no right to return or exchange the licensed software. In general, revenue associated with perpetual licenses is recognized upon the later of the effective date of the license or delivery of the licensed product.

Persuasive evidence of an arrangement – Generally, we use a contract signed by the customer as evidence of an arrangement for subscription and term licenses and hardware leases. If a contract signed by the customer does not exist, we have historically used a purchase order as evidence of an arrangement for perpetual licenses, hardware sales, maintenance renewals and small fixed-price service projects, such as training classes and small methodology service engagements of approximately $10,000 or less. For all other service engagements, we use a signed professional services agreement and a statement of work to evidence an arrangement. In cases where both a signed contract and a purchase order exist, we consider the signed contract to be the most persuasive evidence of the arrangement. Sales through our distributors are evidenced by a master agreement governing the relationship, together with binding purchase orders from the distributor on a transaction-by-transactio n basis.

Product delivery – Software and the corresponding access keys are generally delivered to customers electronically. Electronic delivery occurs when we provide the customer access to the software. Occasionally, we will deliver the software on a compact disc with standard transfer terms of free-on-board, or F.O.B., shipping point. Our software license agreements generally do not contain conditions for acceptance. With respect to hardware, delivery of an entire system is deemed to occur upon its successful installation. For certain hardware products, installation is the responsibility of the customer, as the system is fully functional at the time of shipment. For these products, delivery is deemed to be complete when the products are shipped with freight terms of F.O.B. shipping point.

For customers who purchase eDA Gold or eDA Platinum Cards, delivery occurs when the customer has been provided with access codes that allow the customer to download the software pursuant to the terms of the software license agreement.

Fee is fixed or determinable – We assess whether a fee is fixed or determinable at the outset of the arrangement, primarily based on the payment terms associated with the transaction. We have established a history of collecting under the original contract without providing concessions on payments, products or services. For our installment contracts that do not include a substantial up front payment, we only consider that a fee is fixed or determinable if the arrangement has payment periods that are equal to or less than the term of the licenses and the payments are collected in equal or nearly equal installments, when evaluated over the entire term of the arrangement. We have a history of collecting receivables under installment contracts of up to five years.

Significant judgment is involved in assessing whether a fee is fixed or determinable. We must also make these judgments when assessing whether a contract amendment to a term arrangement (primarily in the context of a license extension or renewal) constitutes a concession. Our experience has been that we are able to determine whether a fee is fixed or determinable for term licenses. While we do not expect that experience to change, if we no longer were to have a history of collecting under the original contract without providing concessions on term licenses, revenue from term licenses would be required to be recognized when payments under the installment contract become due and payable. Such a change could have a material impact on our results of operations.

Collection is probable – We assess the probability of collecting from each customer at the outset of the arrangement based on a number of factors, including the customer’s payment history and its current creditworthiness. We have concluded that collection is not probable for license arrangements executed with customers in certain countries. If in our judgment collection of a fee is not probable, we defer the revenue until the uncertainty is removed, which generally means revenue is recognized upon receipt of cash payment. Our experience has been that we are able to estimate whether collection is probable. While we do not expect that experience to change, if we were to determine that collection is not probable for any license arrangement, particularly those with installment payment terms, revenue from such license would be recognized generally upon the receipt of cash payment. Such a change could have a material impact on our results of operations.

Vendor-specific objective evidence of fair value – Our VSOE for certain product elements of an arrangement is based upon the pricing in comparable transactions when the element is sold separately. VSOE for maintenance is generally based upon the customer’s stated annual renewal rates. VSOE for services is generally based on the price charged when the services are sold separately. For multiple element arrangements, VSOE must exist to allocate the total fee among all delivered and undelivered elements of a term or perpetual license arrangement. If VSOE does not exist for all elements to support the allocation of the total fee among all delivered and undelivered elements of the arrangement, revenue is deferred until such evidence does exist for the undelivered elements, or until all elements are delivered, whichever is earlier. If VSOE of all undelivered elements exists but VSOE does not exist for one or

more delivered elements, revenue is recognized using the residual method. Under the residual method, the VSOE of the undelivered elements is deferred, and the remaining portion of the arrangement fee is recognized as revenue as the elements are delivered. Our experience has been that we are able to determine VSOE for maintenance and time-based services, but not for product.

Finance fee revenue – Finance fees result from discounting to present value the product revenue derived from our installment contracts in which the payment terms extend beyond one year from the effective date of the contract. Finance fees are recognized using a method that approximates the effective interest method over the relevant license term and are classified as product revenue. Finance fee revenue represented approximately 2% of total revenue for each of the years ended December 29, 2007, December 30, 2006 and December 31, 2005. Upon the sale of an installment contract, we recognize the remaining finance fee revenue associated with the installment contract.

Services revenue – Services revenue consists primarily of revenue received for performing design and methodology services. These services are not related to the functionality of the products licensed. Revenue from service contracts is recognized either on the time and materials method, as work is performed, or on the percentage-of-completion method. For contracts with fixed or not-to-exceed fees, we estimate on a monthly basis the percentage-of-completion, which is based on the completion of milestones relating to the arrangement. We have a history of accurately estimating project status and the costs necessary to complete projects. A number of internal and external factors can affect our estimates, including labor rates, utilization and efficiency variances and specification and testing requirement changes. If different conditions were to prevail such that accurate estimates could not be made, then the use of the completed contract method would be required and the recognition of all revenue and costs would be deferred until the project was completed. Such a change could have a material impact on our results of operations.

Accounting for income taxes

We provide for the effect of income taxes in our Consolidated Financial Statements in accordance with SFAS No. 109, “Accounting for Income Taxes” and FIN No. 48.

Under SFAS No. 109, income tax expense or benefit is recognized for the amount of taxes payable or refundable for the current year, and for deferred tax assets and liabilities for the tax consequences of events that have been recognized in an entity’s financial statements or tax returns. We must make significant assumptions, judgments and estimates to determine our current provision for income taxes, our deferred tax assets and liabilities and any valuation allowance to be recorded against our deferred tax assets. Our judgments, assumptions and estimates relating to the current provision for income taxes include the geographic mix and amount of income, our interpretation of current tax laws, and possible outcomes of current and future audits conducted by foreign and domestic tax authorities. Our judgments also include anticipating the tax positions we will take on tax returns prior to actually preparing and filing the tax returns. Changes in our business, tax laws or our interpretation of tax laws, and developments in current and future tax audits, could significantly impact the amounts provided for income taxes in our results of operations, financial position or cash flows. Our assumptions, judgments and estimates relating to the value of our net deferred tax assets take into account predictions of the amount and category of future taxable income from various sources, including tax planning strategies that would, if necessary, be implemented to prevent a loss carryforward or tax credit carryforward from expiring unused. Actual operating results or other events that cause us to change our expectations of the amount and category of income in future years could render our current assumptions, judgments and estimates of recoverable net deferred taxes inaccurate, thus materially affecting our consolidated financial position or results of operations.

Under FIN No. 48, we may only recognize an income tax position in our financial statements that we judge is “more likely than not” to be sustained solely on its technical merits in a tax audit including resolution of any related appeals or litigation processes. To make this judgment, we must interpret the application of complex and sometimes ambiguous tax laws, regulations, and practices. If an income tax position meets the “more likely than not” recognition threshold, then we must measure the amount of the tax benefit to be recognized by determining the largest amount of tax benefit that has a greater than a 50% likelihood of being realized upon effective settlement with a taxing authority that has full knowledge of all of the relevant facts. It is inherently difficult and subjective to estimate such amounts, as this requires us to determine the probability of various possible settlement outcomes. To determine if a tax position is effectively settled, we must also estimate the likelihood that a taxing authority would review a tax position after a tax examination had otherwise been completed. We must also determine when it is



reasonably possible that the amount of unrecognized tax benefits will significantly increase or decrease in the 12 months after each reporting date. These judgments are difficult because a taxing authority may change its behavior as a result of our disclosures in our financial statements that are based on the requirements of FIN No. 48. We must re-evaluate our income tax positions on a quarterly basis to consider factors such as changes in facts or circumstances, changes in tax law, effectively settled issues under audit, and new audit activity. Such a change in recognition or measurement would result in recognition of a tax benefit or an additional charge to the tax provision.

Valuation of stock-based awards

We account for stock-based compensation in accordance with the fair value recognition provisions of SFAS No. 123R, “Share-Based Payment.” Under SFAS No. 123R, stock-based compensation expense is measured at the grant date based on the value of the award and is recognized as expense over the vesting period. Determining the fair value of stock-based awards at the grant date requires judgment, including estimating the following:


• Expected volatility of our stock;
• Expected term of stock options;
• Risk-free interest rate for the period;
• Expected dividends, if any; and
• Expected forfeitures.

The computation of the expected volatility assumption used in the Black-Scholes pricing model for option grants is based on implied volatility calculated using the volatility of publicly traded options for our common stock. We use this approach to determine volatility because:


• Options for our common stock are actively traded;
• The market prices of both the traded options and underlying shares are measured at a similar point in time to each other and on a date reasonably close to the grant date of the employee stock options;
• The traded options have exercise prices that are both near-the-money and close to the exercise price of the employee stock options; and
• The remaining maturities of the traded options on which the estimate is based are at least one year.

When establishing the expected life assumption, we review annual historical employee exercise behavior with respect to option grants having similar vesting periods. In addition, judgment is required in estimating the amount of stock-based awards that we expect to be forfeited. We calculate a separate expected forfeiture rate for both stock options and restricted stock issuances based on historical trends. The valuation of all options and the expected forfeiture rates for options and restricted stock are calculated based on one employee pool as there is no significant difference in exercise behavior between classes of employees. Of the $101.4 million of stock-based compensation expense recorded during 2007, we used the current year valuation assumptions described above for $17.8 million of our 2007 stock-based compensation expense for options granted during 2007, and we used prior year valuation assumptions for $31.2 million of our 2007 stock-based compensation expense for options granted prior to 2007. In addition, we expensed $42.8 million in 2007 related to restricted stock and $9.6 million related to the performance-based bonus plan described below.

Judgment is also required to estimate the attainment of certain predetermined performance goals for a performance-based bonus plan under which payments may be made in our common stock. Each period, we estimate the most likely outcome of such performance goals and recognize any related stock-based compensation expense. The amount of stock-based compensation expense recognized in any one period can vary based on the attainment or estimated attainment of the various performance goals. If such performance goals are not met, no compensation expense is recognized and any previously recognized compensation expense is reversed.

If actual results differ significantly from these estimates, stock-based compensation expense and our results of operations could be materially affected.

Results of Operations

We primarily generate revenue from licensing our EDA software, selling or leasing our hardware technology, providing maintenance for our software and hardware and providing design and methodology services. We principally utilize three license types: subscription, term and perpetual. The different license types provide a customer with different terms of use for our products, such as:


• The right to access new technology;
• The duration of the license; and
• Payment terms.

Customer decisions regarding these aspects of license transactions determine the license type, timing of revenue recognition and potential future business activity. For example, if a customer chooses a fixed term of use, this will result in either a subscription or term license. A business implication of this decision is that, at the expiration of the license period, the customer must decide whether to continue using the technology and therefore renew the license agreement. Because larger customers generally use products from two or more of our five product groups, rarely will a large customer completely terminate its relationship with us at expiration of the license. See the discussion under the heading “Critical Accounting Estimates” above for an additional description of license types and timing of revenue recognition.

Although we believe that pricing volatility has not generally been a material component of the change in our revenue from period to period, we believe that the amount of revenue recognized in future periods will depend on, among other things, the competitiveness of our new technology, the length of our sales cycle, and the size, duration, terms, type and timing of our:


• Contract renewals with existing customers;
• Additional sales to existing customers; and
• Sales to new customers.

A substantial portion of our total revenue is recognized over multiple periods. However, a significant portion of our product revenue is recognized upon delivery of licensed software, which generally occurs upon the later of the effective date of the arrangement or delivery of the software product.

The value and duration of contracts, and consequently product revenue recognized, is affected by the competitiveness of our products. Product revenue recognized in any period is also affected by the extent to which customers purchase subscription, term or perpetual licenses, and the extent to which contracts contain flexible payment terms. The timing of revenue recognition is also affected by changes in the extent to which existing contracts contain flexible payment terms and by changes in contractual arrangements with existing customers (e.g., customers transitioning from subscription license arrangements to term license arrangements).

Revenue and Revenue Mix

We analyze our software and hardware businesses by product group, combining revenues for both product and maintenance because of their interrelationship. We have formulated a design solution strategy that combines our design technologies into “platforms,” which are included in the various product groups described below.

Our product groups are:

Functional Verification: Products in this group, which include the Incisive functional verification platform, are used to verify that the high level, logical representation of an IC design is functionally correct.

Digital IC Design: Products in this group, which include the Encounter digital IC design platform, are used to accurately convert the high-level, logical representation of a digital IC into a detailed physical blueprint and then detailed design information showing how the IC will be physically implemented. This data is used for creation of the photomasks used in chip manufacture.

Custom IC Design: Our custom design products, which include the Virtuoso custom design platform, are used for ICs that must be designed at the transistor level, including analog, radio frequency, memories, high performance digital blocks and standard cell libraries. Detailed design information showing how an IC will be physically implemented is used for creation of the photomasks used in chip manufacture.

System Interconnect Design: This product group consists of our PCB and IC package design products, including the Allegro and OrCAD products. The Allegro system interconnect design platform enables consistent co-design of interconnects across ICs, IC packages and PCBs, while the OrCAD line focuses on cost-effective, entry-level PCB solutions.

Design for Manufacturing: Included in this product group are our physical verification and analysis products. These products are used to analyze and verify that the physical blueprint of the integrated circuit has been constructed correctly and can be manufactured successfully.

Revenue by Year

2007 compared to 2006

Product revenue was higher in 2007, as compared to 2006, primarily because of increased revenue from licenses for Digital IC Design, Functional Verification and Custom IC Design products, partially offset by a small decrease in revenue from licenses for DFM products. Digital IC Design was the fastest growing platform in 2007.

MANAGEMENT DISCUSSION FOR LATEST QUARTER

Results of Operations

We primarily generate revenue from licensing our EDA software, selling or leasing our hardware technology, providing maintenance for our software and hardware and providing design and methodology services. We principally utilize three license types: subscription, term and perpetual. The different license types provide a customer with different terms of use for our products, such as:


• The right to access new technology;
• The duration of the license; and
• Payment terms.

Customer decisions regarding these aspects of license transactions determine the license type, timing of revenue recognition and potential future business activity. For example, if a customer chooses a fixed term of use, this will result in either a subscription or term license. A business implication of this decision is that, at the expiration of the license period, the customer must decide whether to continue using the technology and therefore renew the license agreement. Because larger customers generally use products from two or more of our five product groups, rarely will a large customer completely terminate its relationship with us at expiration of the license. See the discussion under the heading “Critical Accounting Estimates” in our Annual Report on Form 10-K for the fiscal year ended December 29, 2007 for additional description of license types and timing of revenue recognition.

Although we believe that pricing volatility has not generally been a material component of the change in our revenue from period to period, we believe that the amount of revenue recognized in future periods will depend on, among other things, the competitiveness of our new technology, the length of our sales cycle, and the size, duration, terms, type and timing of our:


• Contract renewals with existing customers;
• Additional sales to existing customers; and
• Sales to new customers.

A substantial portion of our total revenue is recognized over multiple periods. However, a significant portion of our product revenue is recognized upon delivery of licensed software, which generally occurs upon the later of the effective date of the arrangement or delivery of the software product.

The value and duration of contracts, and consequently product revenue recognized, is affected by the competitiveness of our products. Product revenue recognized in any period is also affected by the extent to which customers purchase subscription, term or perpetual licenses, and the extent to which contracts contain flexible payment terms. The timing of revenue recognition is also affected by changes in the extent to which existing contracts contain flexible payment terms and by changes in contractual arrangements with existing customers (e.g., customers transitioning from subscription license arrangements to term license arrangements).

Revenue and Revenue Mix

We analyze our software and hardware businesses by product group, combining revenues for both product and maintenance because of their interrelationship. We have formulated a design solution strategy that combines our design technologies into “platforms,” which are included in the various product groups described below.

Our product groups are:

Functional Verification: Products in this group, which include the Incisive functional verification platform, are used to verify that the high level, logical representation of an IC design is functionally correct.

Digital IC Design: Products in this group, which include the Encounter digital IC design platform, are used to accurately convert the high-level, logical representation of a digital IC into a detailed physical blueprint and then detailed design information showing how the IC will be physically implemented. This data is used for creation of the photomasks used in chip manufacture.

Custom IC Design: Our custom design products, which include the Virtuoso custom design platform, are used for ICs that must be designed at the transistor level, including analog, radio frequency, memories, high performance digital blocks and standard cell libraries. Detailed design information showing how an IC will be physically implemented is used for creation of the photomasks used in chip manufacture.

System Interconnect Design: This product group consists of our printed circuit board, or PCB, and IC package design products, including the Allegro and OrCAD ® products. The Allegro system interconnect design platform enables consistent co-design of interconnects across ICs, IC packages and PCBs, while the OrCAD line focuses on cost-effective, entry-level PCB solutions.

Design for Manufacturing: Included in this product group are our physical verification and analysis products. These products are used to analyze and verify that the physical blueprint of the IC has been constructed correctly and can be manufactured successfully.

Revenue by Period

Product revenue decreased in the three and six months ended June 28, 2008, as compared to the three and six months ended June 30, 2007, primarily because of a challenging economic environment and a longer sales cycle. As a result, product revenue decreased for all product groups, and particularly for Digital IC Design, Design for Manufacturing, Functional Verification and Custom IC Design products.

Our product revenue is affected by the mix of license types executed in any given period. We license software using three different license types: subscription, term and perpetual. Product revenue associated with term and perpetual licenses is generally recognized at the beginning of the license period, whereas product revenue associated with subscription licenses is recognized over multiple periods during the term of the license. Our expected revenue for the second half of fiscal 2008 will decrease due to the slowing and price-conscious environment, as well as changes to our license mix, which will result in a higher proportion of revenue recognized over multiple periods during the term of the license and decreased revenue recognized at the beginning of the license.

We have determined that Product revenue totaling $8.4 million recognized during the three months ended June 28, 2008 should have been recognized during the three months ended March 29, 2008. The effect on the Condensed Consolidated Financial Statements for the three months ended June 28, 2008 and March 29, 2008 is not considered material, and there is no effect to the Condensed Consolidated Financial Statements for the six months ended June 28, 2008.

CONF CALL

Jennifer Jordan

Thank you, Teresa, and welcome to our earnings conference call for the second quarter of 2008. The webcast of this call can be accessed through our website, www.cadence.com and will be archived for one week. With me today are Michael Fister, President and CEO; and Kevin Palatnik, Senior Vice President and CFO.

Please note that today's discussion will contain forward-looking statements, and that our actual results may differ materially from those expectations. For information on the factors that could cause a difference in our results, please refer to our 10-K for the period ended March 29, 2007 and our 10-Q for the period ended March 29, 2008.

The information set forth under the headings cautionary statement regarding forward-looking statements and important information in the earnings press release issued today. In addition to financial results prepared in accordance with Generally Accepted Accounting Principles or GAAP, we will also present certain non-GAAP financial measures today.

Cadence management believes that, in addition to using GAAP results in evaluating our business, it can also be useful to measure results using certain non-GAAP financial measures. Please refer to an earnings press release for discussion of non-GAAP measures, and to both our earnings press release and our website for reconciliation of GAAP and non-GAAP financial measures used in today's discussion.

And with that, I'll turn the call over to Mike Fister.

Mike Fister

Thanks, Jennifer. Good afternoon to everyone has joined us on today's call. I'll begin today's call with some high level comments on the quarter, our business as a whole, and also provide a brief update on our proposal to acquire Mentor Graphics. Then I will turn the call over to Kevin, who will go into more detail in the numbers in our outlook.

Revenue for Q2 was $329 million, and non-GAAP earnings per share were $0.14.

Key business highlights for the quarter include testimonials from several major customers, as well as the announcement of new technology for the systems software space.

Matsushita is deploying Virtuoso 6.1 for both its advance and legacy process nodes. Renesas publicly endorsed our solution for integrated statistical timing and optimization, and are recently followed up with an announcement that they have adopted SoC encounter for their largest and most complex advanced chips.

Broadcom recently increased its capacity using the latest play in three technology, and told us that the palladium n-circuit emulation and Ethernet speed bridge adapters have been key to the system validation efforts for market-leading Ethernet switch products.

This quarter we announced a C-to-Silicon Compiler, which helps customers reduce iterations between system specification and design implementation, and improved designer productivity for IP creation and reuse.

Hitachi and Renesas both provided input into the technology, and are now using it successfully. Although we achieved our Q2 numbers, and had a number of successes with our customers and new technology releases, it was challenging. The impact is slowing and the price conscious economic environment exceeds what we originally anticipated.

Customers are demanding even more flexibility in when, what, and how they purchase software and hardware. Many of our customers are facing uncertainty, or outright slowdowns, in their businesses. Others are choosing to amortize current technology investments, staying with the same process nodes and methodologies longer.

This means new design methodologies using our advanced products are slower to migrate from high-end to gain broad proliferation in the main stream. This invariably puts greater risk into our ability to do incremental business in the second half. And yet other customers are demanding greater flexibility in terms and access due to market conditions in order to close business.

As a result, we made the difficult but necessary decision to lower our outlook, and transition to an approximately 90% rateable license mix. We believe this transition will enable to us keep our focus on the value of our technology, and this decision is the right one for our business over the long-term and for building sustaining strong customer relationships in the future.

Cadence's fundamentals are intact. We have strong customer relationships around the world, and continue to maintain our share of customer spend. We continue to make investments in research and development, and have a robust pipeline of technology. Product rollouts are on track, we'll introduce some of these CDNLive! in September.

We have a talented team committed to the long-term success of our business. Now I would like to take a moment to update you regarding our proposal to acquire Mentor Graphics. As you know, on June 17th, we publicly disclosed our all cash proposal to acquire all the outstanding shares of Mentor Graphics for $16 per share.

We continue to believe that our proposal is extremely compelling for the Mentor Graphics shareholders. Our proposal provides them with the unique opportunity to realize with certainty a significant cash premium value for their investment in Mentor Graphics.

It remains our preference to work cooperatively with Mentor Graphics to complete the acquisition. Although we have not had discussions with Mentor Graphics concerning our acquisition proposal, we continue to communicate to them and their advisors, both privately and publicly, and we want to meet with them immediately to begin substantive discussions regarding our proposal.

That said, we remain committed to the transaction, and are moving this process forward on several fronts. We have commenced the regulatory process and filed the require HSR notices with the US regulatory authorities. We remain confident that proposed transaction will receive all necessary governmental approvals.

Additionally, as of July 11th, Cadence has acquired, through open market transactions, approximately 4.3 million shares of Mentor Graphics. This represents approximately 4.7% of the Mentor's outstanding common stock. We're confident that our HSR filing and ownership stake in Mentor Graphics demonstrate our commitment to this transaction.

We're also in the process of working with our financial advisors to structure the permanent financing for the transaction on the most attractive terms available to us. And let me reiterate that our proposal is not subject to any financing conditions. We continue to believe strongly in this acquisition, and we will do what makes sense for us and our shareholders in making this combination a reality.

I will now turn the call over to Kevin.

Kevin Palatnik

Thanks, Mike. Results for our key operating metrics for Q2 were total revenue of $329 million, non-GAAP operating margin of 15%, and operating cash flow of $77 million. GAAP earnings per share for Q2 was $0.02, compared to $0.20 for Q2 of 2007. Non-GAAP earnings per share for Q2 was $0.14, compared to $0.30 for Q2 of 2007.

Total revenue for the second quarter was $329 million, compared to $391 million for Q2 of 2007, a decrease of 16%. Product revenue was $195 million, maintenance revenue was $100 million, and services revenue was $34 million.

Revenue mix by geography in Q2 was 49% for the Americas, 21% for Europe, 18% for Japan, and 12% for Asia.

Total cost and expenses on a non-GAAP basis for Q2 were $280 million, flat when compared to Q2 of 2007. Non-GAAP operating margin for Q2 was 15%, and quarter-end headcount was approximately 5,100.

Total DSOs for Q2 decreased to 139 days from 176 days in Q1, and quality receivables remains high, with less than 1% of receivables 90 days past due.

Operating cash flow for Q2 was $77 million, compared to $101 million for the second quarter of 2007. Capital expenditures for Q2 were $36 million. Cadence did not repurchase any common stock in Q2, and approximately $412 million remains under our current stock repurchase authorization. Cash and cash equivalents were $837 million at quarter-end.

Now, I will turn to our outlook for Q3 and the year. The outlook reflects the shift to a 90% ratable mix, and lower business levels for the remainder of the year. For Q3, we expect revenue to be in the range of $235 million to $245 million. GAAP EPS should be in the range of a loss of $0.25 to $0.27, and non-GAAP EPS in the range of a loss of $0.09 to $0.11.

For the year 2008, we expect revenue to be in the range of $1.12 billion to $1.14 billion. We expect year-end backlog to be approximately $2 billion with order levels at approximately $1.1 billion.

For 2008, we expect weighted average contract life to be in the range of three to four years. We expect to be breakeven for the non-GAAP operating margin on an annual basis for 2008. GAAP EPS should be in the range of a loss of $0.50 to $0.54, and non-GAAP EPS in the range of a positive $0.01 to $0.05.

Other income for 2008 should be in the range of $12 million to $16 million. For 2008, we expect to generate operating cash flow of approximately $175 million, down from our prior estimate of $300 million, due primarily to lower business levels and to a lesser extent fewer receivable sales. We expect DSOs to be approximately 125 days at the close of 2008.

Capital expenditures for 2008 should be in the range of $70 million, with an additional $37 million for work to complete our new engineering building. I know it is hard to analyze this software company when it goes through this kind of transition because of the impact the ratable mix has on revenue and operating margin.

Although it is too early to provide specifics on 2009 guidance, I do want to provide some insight for operating cash flow. Our preliminary look at operating cash flow for 2009 suggests that it will be approximately $250 million, with less than 10% coming from receivable sales.

Looking forward, our strategy is to continue to leverage EDA cards. Customers, large and small, continue to embrace our EDA cards as a preferable sale and delivery mechanism for our software. We expect to change to a high ratable mix to contain an increased proportion of platinum cards, as well some as ratable gold cards.

One final point, I believe the reduction in our outlook, and the move to a higher ratable mix is the right change for the business, as we look to the environment and our customer base. Going forward, we'll have more flexibility to provide the right solution to customers when they need it and value it appropriately.

SHARE THIS PAGE:  Add to Delicious Delicious  Share    Bookmark and Share



 
Icon Legend Permissions Topic Options
You can comment on this topic
Print Topic

Email Topic

16242 Views