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Article by DailyStocks_admin    (11-26-07 07:22 AM)

The Daily Magic Formula Stock for 11/23/2007 is Applied Materials Inc. According to the Magic Formula Investing Web Site, the ebit yield is 11% and the EBIT ROIC is 75 - 100%

Dailystocks.com only deals with facts, not biased journalism. What is a better way than to go to the SEC Filings? It's not exciting reading, but it makes you money. We cut and paste the important information from SEC filings for you to get started on your research on a specific company.


Dailystocks.com makes NO RECOMMENDATIONS whatsoever, and provides this for informational purpose only.

BUSINESS OVERVIEW

Organized in 1967, Applied, a Delaware corporation, develops, manufactures, markets and services fabrication equipment for the worldwide semiconductor and semiconductor-related industries. Customers for these products include manufacturers of semiconductor chips and wafers, flat panel displays, and other electronic devices such as solar photovoltaic (PV) cells. These customers use what they manufacture in their own products or sell them to other companies for use in advanced electronic components.

During fiscal 2006, Applied made certain changes to its internal financial reporting structure and, as a result, is reporting four segments: Silicon, Fab Solutions, Display, and Adjacent Technologies. A summary of net sales, operating income, depreciation/amortization , capital expenditures and assets for reportable segments is found in Note 10 to the Consolidated Financial Statements. A discussion of factors potentially affecting Applied’s operations is set forth under “Risk Factors” in Item 1A, which is incorporated herein by reference.

Silicon Segment

Applied’s Silicon segment comprises a wide range of manufacturing equipment used to fabricate semiconductor chips. Applied currently offers systems that perform most of the primary steps in the chip fabrication process, including: atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical plating (ECP), etch, ion implantation, rapid thermal processing (RTP), chemical mechanical planarization (CMP), wafer wet cleaning, wafer metrology and inspection, and systems that etch, measure and inspect circuit patterns on masks used in the photolithography process.

Most chips are built on a silicon wafer base and include a variety of circuit components, such as transistors and other devices, that are connected by multiple layers of wiring (interconnects). To build a chip, the transistors, capacitors and other circuit components are first created on the surface of the wafer by performing a series of processes to deposit and selectively remove successive film layers. Similar processes are then used to build the layers of wiring structures on the wafer. As the density of the circuit components increases to enable greater computing power in the same or smaller area, the complexity of building the chip also increases, necessitating more process steps to form smaller structures and more intricate wiring schemes. A typical, simplified process sequence for building the wiring portion of chips involves initially depositing a dielectric film layer onto the base layer of circuit components using a CVD system. An etch system is then used to create openings and patterns in the dielectric layer. To form the metal wiring, these openings and patterns are subsequently filled with conducting material using PVD and/or ECP technologies. A CMP step then polishes the wafer to achieve a flat surface. Additional deposition, etch and CMP steps are then performed to build up the layers of wiring needed to complete the interconnection of the circuit elements to form the chip. Advanced chip designs require about 500 steps involving these and other processes to complete the manufacturing cycle.

Over time, the semiconductor industry has migrated to increasingly larger wafers to build chips. The predominant wafer size used for volume production today is 200 millimeter (mm), or eight-inch, wafers, but a substantial number of advanced fabs now use 300mm, or 12-inch, wafers to gain the economic advantages of a larger surface area. The majority of new fab capacity is 300mm. Applied offers a comprehensive range of systems and, through its Fab Solutions segment, products and services to support 200mm and 300mm wafer processing.

A majority of process steps used in chipmaking are performed to build the interconnect, a complex matrix of microscopic wires that carry electrical signals to connect the transistor and capacitor components of a chip. While some customers are still using aluminum as the main conducting material for the interconnect, many have transitioned to copper. Copper has lower resistance than aluminum and can carry more current in a smaller area. Applied is the leading supplier of systems for manufacturing copper-based chips, and supplies systems for depositing, etching and planarizing the copper interconnect layers.

Complementing the transition to copper to improve chip speed is the use of low dielectric constant (low k) films to replace silicon dioxide material as the insulator between the copper wiring structures. Applied leads the industry in providing low k dielectric systems to chip manufacturers and many of these customers use the Company’s

Applied Producer Black Diamond ® system in volume production. Applied’s second-generation system for low k dielectric film, the Applied Producer Black Diamond II, further reduces the dielectric constant to enhance the speed of customers’ most advanced chip designs.

The transistor portion of the chip is another area in which semiconductor manufacturers are improving their device designs to enhance speed. Applied has the industry’s largest portfolio of technically advanced products for building smaller and faster transistors. One such area is strain engineering, a technique that stretches or compresses the space between atoms, allowing current to flow more quickly, thus greatly enhancing chip performance. Applied leads the equipment industry in providing solutions to enable these applications with products such as its Applied Producer Stress Nitride, Applied Producer HARP (high aspect ratio process) and Applied Centura Epi systems.

Most of Applied’s products are single-wafer systems with multiple process chambers attached to a base platform. Each wafer is processed separately in its own environment, allowing precise process control, while the system’s multiple chambers enable simultaneous, high productivity manufacturing. Applied sells most of its single-wafer, multi-chamber systems on four basic platforms: the Centura ® , the Endura ® , the Producer ® and the Vantage ® . These platforms currently support ALD, CVD, PVD, etch and RTP technologies.

The following summarizes Applied’s portfolio of products and their associated process technology areas reported under its Silicon segment.

Deposition

Deposition is a fundamental step in fabricating a chip. During deposition, layers of dielectric (an insulator), barrier, or electrically conductive (typically metal) films are deposited or grown on a wafer. Applied currently provides equipment to perform the four main types of deposition: ALD, CVD, PVD and ECP. In addition, Applied’s RTP systems can be used to perform certain types of dielectric deposition.

Atomic Layer Deposition

ALD is an emerging technology in which atoms are deposited one layer at a time to build chip structures. This technology enables customers to fabricate thin films of either conducting or insulating material with uniform coverage in sub-nanometer sized structures. Applied offers ALD chambers for depositing tungsten and tantalum nitride films. The Applied Endura iCuBS tm product is the industry’s first system to integrate ALD and PVD chambers on a single platform for depositing critical barrier and seed layers in copper interconnects. The Applied Centura iSprint tm Tungsten system (iSprint) combines an ALD chamber, which deposits a tungsten nucleation film, with a CVD tungsten bulk fill process in one system. The iSprint is used to form contact structures that connect the transistors to the wiring areas of the chip.

Chemical Vapor Deposition

CVD is used by customers to deposit dielectric and metal films on a wafer. During the CVD process, gases that contain atoms of the material to be deposited react on the wafer surface, forming a thin film of solid material. Films deposited by CVD may be silicon oxide, single-crystal epitaxial silicon, amorphous silicon, silicon nitride, dielectric anti-reflective coatings, low k dielectric (for highly efficient insulating materials), aluminum, titanium, titanium nitride, polysilicon, tungsten, refractory metals or silicides. Applied offers the following CVD products and technologies:

The Applied Producer CVD system — This high-throughput platform features Twin-Chamber tm modules that have two single-wafer process chambers per unit. Up to three Twin-Chamber modules can be mounted on each Producer platform, giving it a simultaneous processing capacity of six wafers. Many dielectric CVD processes can be performed on this platform. Key processes that help chipmakers extend their current lithography tools are the Applied Producer APF-e tm (advanced patterning film) and the Applied Producer DARC ® (dielectric anti-reflective coating) films. Together, they provide a film stack with the precise dimensional control and compatibility needed to cost-effectively pattern nano-scale features without additional integration complexity.

The Applied Centura Ultima HDP-CVD ® system — High-density plasma CVD (HDP-CVD) is used to fill very small, deep spaces (gap-fill) with dielectric film. This product is used by a number of major integrated circuit manufacturers for gap-fill applications, including the deposition of silicon oxides in substrate isolation structures, contacts and interconnects.

Low k Dielectric Films — Many integrated circuit manufacturers are now incorporating new low k dielectric materials in their copper-based chip designs to further improve interconnect speed. The Applied Producer Black Diamond CVD low k system is being used by several customers in volume production to produce some of the industry’s most advanced devices. Using conventional CVD equipment, the Black Diamond product provides customers with a proven, cost-effective way to transition to this new material. The Applied Producer Black Diamond II is a second-generation dielectric that provides a lower k-value film for building faster 65 nanometer (nm) generation and below chip designs. A complementary low k dielectric, called the Applied Producer BLOk tm (Barrier low k), enables the complete, multi-layer dielectric structure to benefit from low k technology.

Epitaxial Deposition — Epitaxial silicon (epitaxy or epi) is a layer of pure silicon grown in a uniform crystalline structure on the wafer to form a high quality base for the device circuitry. Epi technology is used in an increasing number of integrated circuit devices in both the wafer substrate and transistor areas of a chip to enhance speed. The Applied Centura Epi system integrates pre- and post-epi processes on the same system to improve film quality and reduce production costs. This system is also being used for silicon-germanium epi technology, which can reduce power usage and increase speed in certain types of advanced chips. For emerging transistor designs, the Applied Centura RP Epi system offers selective epi processes to enable faster transistor switching without the need to shrink the scale of the device.

Polysilicon Deposition — Polysilicon is a type of silicon used to form portions of the transistor structure within the integrated circuit device. The Applied Centura Polygen tm LPCVD (low pressure chemical vapor deposition) system is a single-wafer, multi-chamber product that deposits thin, polysilicon films at high temperatures to create transistor gate structures. To address the challenging requirements of shrinking transistor gate structures, the Applied Centura DPN Gate Stack system integrates chambers for decoupled plasma nitridation (DPN), RTP anneal and polysilicon deposition on one platform to enable superior film quality and material properties.

Silicon Nitride Deposition — The Applied Centura SiNgen ® Plus LPCVD system is a single-wafer, high-temperature system that deposits silicon nitride films for transistor applications. This system minimizes the amount of time the wafer is exposed to high temperatures and reduces particles while improving operating cost and productivity in critical transistor nitride layers.

Aluminum Deposition — In fiscal 2006, the Company introduced its Applied CVD Al (aluminum) process technology for building high-density interconnects in Flash and DRAM memory chips. Aluminum continues to be the material used by many memory manufacturers for interconnects. This advanced process, for sub-90nm generations, enables customers to replace tungsten structures with aluminum to achieve faster chips with fewer steps and less cost.

Tungsten Deposition — Tungsten is used in the contact area of a chip that connects the transistors to the wiring circuitry. In aluminum-based devices, tungsten is also used in the structures that connect the multiple layers of aluminum wiring. The Company has two products for depositing tungsten: the Applied Centura Sprint ® Tungsten CVD system for 90nm and below devices and the Applied Centura iSprint ALD/CVD system for more advanced applications. The latter product combines ALD technology and CVD chambers on the same platform.

Physical Vapor Deposition

PVD, also called sputtering, is a physical process in which atoms of a gas, such as argon, are accelerated toward a metal target. The metal atoms chip off, or sputter away, and are then deposited on the wafer. Applied leads the industry in PVD technology with its Applied Endura PVD system. This system offers a broad range of advanced deposition processes, including aluminum, aluminum alloys, cobalt, titanium/titanium nitride, tantalum/tantalum nitride, tungsten/tungsten nitride, nickel, vanadium and copper (Cu).

The Applied Endura CuBS (copper barrier/seed) PVD system is widely used by customers for fabricating copper-based chips. Using PVD technology, the system deposits critical layers that prevent copper material from entering other areas of the device and primes the structure for the subsequent deposition of bulk copper by electrochemical plating. In fiscal 2006, Applied enhanced this system with new pre-clean chamber technology, extending the system’s capabilities to 45nm-generation and below copper-low k interconnects.

The Applied Endura system’s highly flexible, multi-chamber architecture allows the integration of multiple PVD processes or combinations of metal CVD and PVD technologies on the same system. In addition to the integrated Applied Endura iCuBS ALD/PVD system (discussed in the Atomic Layer Deposition section), the Applied Endura iLB tm (integrated liner barrier) system combines a PVD chamber for depositing titanium with a CVD chamber for titanium nitride deposition to form critical lining layers of interconnect structures. These structures are subsequently filled with tungsten, aluminum or other materials. In fiscal 2006, Applied announced significant advances to its Endura iLB system to meet the requirements of customers’ leading-edge device designs.

Electrochemical Plating

Electrochemical plating is a process by which metal atoms from a chemical fluid (an electrolyte) are deposited on the surface of an immersed object. Its main application in the semiconductor industry is to deposit copper in interconnect wiring structures. This process step follows the deposition of barrier and seed layers that prevent the copper from contaminating other areas of the device and improve the adhesion of the copper film.

The Applied SlimCell tm ECP (electrochemical plating) system offers a small-volume cell design that enables a reduction in defect levels compared to conventional systems while reducing chemical consumption.

Etch

Etching is used many times throughout the integrated circuit manufacturing process to selectively remove material from the surface of a wafer. Before etching begins, the wafer is coated with a light-sensitive film, called photoresist. A photolithography process then projects the circuit pattern onto the wafer. Etching removes material only from areas dictated by the photoresist pattern. Applied offers a full range of systems for etching dielectric, metal and silicon films to meet the requirements of sub-100nm processing.

For dielectric applications, the Applied Centura eMax ® system etches a broad range of dielectric films in the contact and interconnect regions of the chip. Applied’s Producer Etch system utilizes the Company’s Twin-Chamber Producer platform concept to target cost-sensitive dielectric etch applications in 90nm and below design geometries. To address advanced low k etch applications, the Applied Centura Enabler ® Etch system performs etch, strip and clean steps in a single chamber. The Enabler’s all-in-one capability streamlines the process flow for 65nm and below chip designs and significantly reduces operating costs.

The Applied Centura AdvantEdge tm Silicon Etch system offers chipmakers high precision gate etching for 65nm and 45nm-generation devices. For etching metals, Applied launched the Applied Centura AdvantEdge Metal Etch system in fiscal 2006. This system enables customers to extend aluminum interconnect technology to sub-70nm dimensions for Flash and DRAM memory applications.

Ion Implantation

During ion implantation, silicon wafers are bombarded by a beam of ions, called dopants, that penetrate (or implant) the film surface to a desired depth. The implantation step is used during transistor fabrication to change electrical properties of a material and achieve a particular electrical performance. Low-energy, high current implant technology is important to enabling the fabrication of smaller structures, which contributes to faster transistor performance. The Applied Quantum ® X Plus Implant system provides chipmakers with a production-worthy, single-wafer, high-current implanter that enables transistor scaling beyond the 45nm node. The Quantum X Plus system’s fixed beam and precision mechanical scanning system provide precise energy control and low defect levels to deliver the process technology needed to achieve the most difficult and critical implants.

Rapid Thermal Processing

RTP is a process in which a wafer is subjected to rapid bursts of intense heat that can take the wafer from room temperature to more than 1,000 degrees Celsius in less than 10 seconds. A rapid thermal process is used mainly for modifying the properties of deposited films. The Applied Centura Radiance ® Plus and Applied Vantage Radiance Plus RTP systems feature the same advanced RTP technology with differing platform designs. While the multi-chamber Centura platform offers exceptional process flexibility, the streamlined two-chamber Vantage platform is designed for dedicated high-volume manufacturing. These single-wafer RTP systems are also used for growing high quality oxide and oxynitride films, deposition steps that traditional large batch furnaces can no longer achieve with the necessary precision and control. For flash memory applications, the Applied Vantage RadOx tm system deposits high-performance transistor gate oxides with high productivity and low operating cost.

Chemical Mechanical Planarization

The CMP process removes material from a wafer to create a flat (planarized) surface. This process allows subsequent photolithography patterning steps to occur with greater accuracy and enables film layers to build with minimal height variations. The Company’s 200mm Applied Mirra Mesa ® systems and 300mm Applied Reflexion ® systems led the industry in CMP technology with important features such as integrated cleaning, film measurement and process control capabilities. The Company’s 300mm Applied Reflexion LK Ecmp tm system features proprietary electrochemical mechanical planarization technology to provide a high-performance, cost-effective and extendible solution for copper/low k interconnects at the 65nm node and below. The Ecmp system removes bulk copper at a high rate by electric charge, making it ideal for fragile ultra-low k films.

Metrology and Wafer Inspection

Applied offers several types of products that are used to measure and inspect the wafer during various stages of the fabrication process:

Critical Dimension and Defect Review Scanning Electron Microscopes (CD-SEMs and DR-SEMs)

Scanning electron microscopes (SEMs) use an electron beam to form images of microscopic features, or critical dimensions (CDs), of a patterned wafer at extremely high magnification. Applied’s SEM products or systems provide customers with full automation, along with the high accuracy and sensitivity needed for measuring very small CDs. The Applied VeritySEM tm Metrology system uses proprietary SEM imaging technology to enable precise control of the lithography and etching processes. The VeritySEM measures CDs with less than 5 angstrom precision — a requirement for 45nm device production — and incorporates automation and software advancements for significantly higher throughput in production. The Company’s OPC Check tm software for the VeritySEM system performs automated qualification of OPC-based (optical proximity correction) chip designs, significantly reducing mask (see Mask Making section below) verification time over conventional manual methods.

DR-SEMs review defects on the wafer (such as particles, scratches or residues) that are first located by a defect detection system and then classify the defects to identify their source. The high-throughput, fully automatic Applied SEMVision tm G3 Defect Analysis products enable customers to use this technology as an integral part of their production lines to analyze defects as small as 30nm with industry-leading throughput. The Applied SEMVision G3 FIB integrates advanced defect review SEM capability with automated focused ion beam (FIB) technology in one system. The FIB provides a cross-sectional view of the defects reviewed by the SEM, enabling chipmakers to analyze the defects in minutes as part of their in-line review process.

Wafer Inspection

Using laser-based technology, defects can be detected on patterned wafers (wafers with printed circuit images) as they move between processing steps. Defects include particles, open circuit lines, and shorts between lines. Incorporating key advances in imaging technology, the Applied ComPlus 3T tm Inspection system, for darkfield applications, detects defects in devices with design rules of 65nm and below with the high speed required for customers’ volume production lines. The Applied UVision tm Inspection system is the industry’s first laser-based 3D brightfield tool. Utilizing multi-beam, deep ultraviolet (DUV) laser illumination and high efficiency detectors, the UVision system uncovers critical defects on the wafer that have not been detected before by other inspection systems, enabling customers to rapidly resolve performance-limiting defect issues and achieve greater chip yields.

Mask Making

Masks are used by photolithography systems to transfer microscopic circuit designs onto wafers. Since an imperfection in a mask may be replicated on the wafer, the mask must be virtually defect-free. Applied provides systems for etching, measuring and inspecting masks. The Applied Tetra II Mask etch system is based on the Company’s production-proven decoupled plasma source (DPS) wafer etch technology and is the semiconductor industry’s most advanced etch tool for fabricating masks. The Applied RETicle SEM system, built on Applied’s proven CD-SEM platform, measures virtually all mask types with sub-1nm precision, meeting the requirements of the industry’s most advanced masks.

Fab Solutions Segment

Through its Fab Solutions segment, Applied provides products and services designed to improve the performance and productivity of semiconductor manufacturers’ fab operations. These products embody the in-depth expertise and best known methods of Applied’s extensive global support infrastructure.

Fab Solutions serves a critical role in Applied’s ability to continuously support customers’ production requirements. Approximately 3,100 trained customer engineers and process support engineers are deployed in more than a dozen countries. These engineers are usually located at or near customers’ fab sites and service over 20,000 installed Applied systems and non-Applied systems.

Applied offers a broad range of products to maintain, service and optimize the operations of customers’ fabs. Applied Materials Genuine Parts tm include spare parts manufactured to Applied’s strict technical specifications and quality standards. Applied Certified Service Products tm provide customers with optimized tool performance for improved total cost of ownership and a higher return on investment. Applied also offers remanufactured equipment, product enhancements and technical training for customers.

As part of its eService Solutions, Applied offers FAB300 tm , a manufacturing execution system (MES), to monitor and control fab manufacturing activities. This system is used in semiconductor fabs, test, assembly and packaging facilities, and flat panel display (FPD) manufacturing facilities. Applied also offers a suite of diagnostic software that links hardware, process and service data from different processing systems throughout the fab. The Applied NeXus tm SPC product is a new diagnostic tool that performs split-second analysis of process conditions in Applied’s processing systems.

Metron Technology, Inc. (Metron), a wholly-owned subsidiary of Applied Materials, offers a range of products and services for fab operations support. Metron’s products include fab and sub-fab systems, wafer management services, chamber performance services, gas and fluid handling components, and other services that are critical to semiconductor manufacturing. With Metron’s acquisition of ChemTrace in fiscal 2006, Metron now offers chipmakers a wide range of services to analyze and identify the sources of surface or airborne contamination. Metron also offers EcoSys ® treatment systems to address a broad spectrum of semiconductor abatement applications. These energy-saving solutions enable chipmakers to meet their most stringent environmental goals.

Display Segment

Applied also manufactures and services equipment to fabricate flat panel displays (FPDs). These systems are used by FPD manufacturers to build and test thin-film transistor liquid crystal display (TFT-LCD) panels for televisions, computer displays and other consumer-oriented electronic applications. While similarities exist between the technologies utilized in chipmaking and display fabrication, there are significant differences, such as in the size and composition of the substrate (wafer vs. panel). FPD panels can be more than 70 times larger in area than today’s largest wafers (300mm diameter), and wafers are made of silicon, while FPD panels are made of glass.

Applied supplies a wide range of systems that process and test many different panel sizes. To meet consumers’ growing demand for larger, more cost-efficient LCD TVs, FPD manufacturers have continually increased the size of panels that can be processed. Leading-edge substrates, sized at 2.2 x 2.5 meters (m), now processed by Generation (Gen) 8.5 systems, are designed to enable the production of up to six 55-inch LCD TV screens. Applied announced three new systems for manufacturing Gen-8.5 panels in October 2006.

The AKT-55K PECVD (plasma-enhanced CVD) system, used for fabricating the transistor layer of Gen-8.5 panels, features Applied’s multi-chamber platform architecture. For fabricating the color filter layer of these panels, Applied offers a fully automated vertical sputtering system, the AKT-NEW ARISTO tm 2200. Applied acquired the NEW ARISTO tm technology during fiscal 2006 as part of its acquisition of Applied Films Corporation (Applied Films).

Complementing these systems, Applied also offers electron beam systems for testing substrates during production for defective pixels and other imperfections. The AKT-55K EBT is a Gen-8.5 tester that features one of the industry’s fastest and most accurate pixel test technology with the lowest operating cost. The electron beam system’s non-contact test technology enables safe testing of high-value LCD TV panels without damaging or scratching the display.

Adjacent Technologies Segment

The acquisition of Applied Films, a supplier of thin film deposition equipment, accelerated Applied’s entry into growing new markets, such as solar PV cells, flexible electronics and energy-efficient glass.

In the solar PV area, Applied offers a suite of manufacturing systems to enable customers to increase the conversion efficiency and yields of their PV devices, thus helping to lower the overall cost per watt for solar electricity. These include equipment as well as processes, material-handling technologies and services to support the manufacture of both crystalline-silicon and thin-film silicon solar cells. Applied’s ATON tm in-line sputtering system provides quality deposition, high throughput and low cost of ownership for both thin-film and multi-or mono-crystalline silicon.

Applied also provides high-performance, roll-to-roll vacuum web coating systems for depositing a wide range of films on flexible substrates for functional, aesthetic or optical properties. The TOPMET tm system is capable of handling substrates in roll widths from 1.25-4.5m with high throughput and low cost of ownership.

Applied offers large-area sputter coating equipment for the production of low-emissivity and solar control architectural glass. The AXL 870 tm coating system is a highly flexible and cost-effective tool that customers can easily reconfigure to produce a variety of products to meet the challenges of a changing market.

MANAGEMENT DISCUSSION FROM LATEST 10K

Introduction

Management’s Discussion and Analysis (MD&A) is intended to facilitate an understanding of Applied’s business and results of operations. This MD&A should be read in conjunction with Applied’s Consolidated Financial Statements and the accompanying Notes to Consolidated Financial Statements included elsewhere in this report. The following discussion contains forward — looking statements and should also be read in conjunction with the cautionary statement set forth at the beginning of this Annual Report on Form 10-K. MD&A consists of the following sections:


• Overview: a summary of Applied’s business, measurements and opportunities.

• Results of Operations: a discussion of operating results.

• Segment Information: a discussion of segment operating results.

• Financial Condition, Liquidity and Capital Resources: an analysis of cash flows, sources and uses of cash, contractual obligations and financial position.

• Critical Accounting Policies: a discussion of critical accounting policies that require the exercise of judgments and estimates.

Overview

Applied develops, manufactures, markets and services semiconductor and semiconductor-related fabrication equipment, providing nanomanufacturing technology tm solutions to the global semiconductor, flat panel display, solar and other industries. Product development and manufacturing activities occur in North America, Europe and Israel. Applied’s broad range of equipment and service products are highly technical and are sold through a direct sales force. Customer demand for spare parts and services is fulfilled through a global spare parts distribution system and trained service engineers located around the world in close proximity to customer sites.

As a supplier to these industries, Applied’s results are primarily driven by worldwide demand for chips and flat panel displays, which in turn depends on end-user demand for electronic products. The industries in which Applied operates are volatile and its results in fiscal 2004 through 2006 reflect this volatility.

Operating results for fiscal 2004 reflected a recovery from a downturn in the semiconductor industry and the global economy, as well as realized savings from Applied’s fiscal 2003 realignment activities. In addition, Applied gained market share in critical areas, including 300mm equipment and copper interconnect, and improved its operational efficiencies.

Fiscal 2005 results reflected a challenging environment as Applied’s customers decreased fab utilization globally and reduced or delayed capital expenditures as a result of excess inventories and slowing demand for chips. In this period, Applied focused on lowering costs, improving efficiencies, reducing cycle time and bringing new products to market. During the fourth quarter of fiscal 2005, customer demand for Applied products began to increase.Customer demand further improved in fiscal 2006, resulting in higher orders and revenue. Fiscal 2006 results reflected a recovery in the semiconductor and semiconductor-related industries and the global economy as end-user demand for electronic products and flat panel displays drove increased customer requirements for advanced silicon and display products. During this period, Applied’s semiconductor customers increased both high-volume production and leading-edge 65nm and 45nm chip development. Results for this period also reflected Applied’s continued focus on cost controls. Improvements in operating performance were offset in part by restructuring and asset impairment charges associated with real estate and facilities disinvestment that commenced during the first fiscal quarter, equity-based compensation expenses and an in-process research and development expense associated with the acquisition of Applied Films Corporation (Applied Films).

During the second half of fiscal 2006, Applied completed certain transactions in support of its long-term growth strategy. Management believes that these transactions will enhance Applied’s ability to extend its nanomanufacturing capabilities into adjacent and new markets, including color filters for flat panel displays, solar cells, flexible electronics, energy-efficient glass and track solutions for semiconductor manufacturing. These transactions included the acquisition of Applied Films, the formation of a joint venture with Dainippon Screen Mfg. Co., Ltd. (Screen), and the purchase of certain parts cleaning and recycling assets in Singapore from UMS Solutions Pte. Ltd. (UMS Solutions), a wholly-owned subsidiary of Norelco UMS Holdings Limited.

Applied’s long-term opportunities depend in part on successful execution of its growth strategy, including increasing market share in existing markets, expanding into related markets, and cultivating new markets and new business models. These opportunities are also subject to many factors, including: (1) global economic conditions; (2) advanced technology and/or capacity requirements of semiconductor manufacturers and their capital investment trends; (3) the profitability of chip and display manufacturers; (4) supply and demand for chips, flat panel displays, solar panels, and related products and services; (5) realization of the anticipated benefits of business combinations; (6) continued investment in research, development and engineering (RD&E); and (7) the relative competitiveness of Applied’s equipment and service products. For these and other reasons set forth in Part 1, Item 1A, “Risk Factors,” Applied’s prior results of operations are not necessarily indicative of future operating results.

Results of Operations

Net Sales

Applied’s business was subject to cyclical industry conditions in fiscal 2004, 2005 and 2006. As a result of these conditions, there were significant fluctuations in Applied’s quarterly new orders and net sales, both within and across the fiscal years. Demand for manufacturing equipment has historically been volatile as a result of sudden changes in chip and flat panel supply and demand and other factors, including rapid technological advances in fabrication processes.

New orders increased to $9.0 billion for fiscal 2004, reflecting a broad-based increase in capital investment in 300mm technology to meet rising demand for chips and flat panel displays. Following the new order trends, net sales increased to $8.0 billion in fiscal 2004, reflecting the fulfillment of higher levels of orders for capital equipment received in prior quarters to support customers’ manufacturing capacity expansion and new technology requirements.

New orders for fiscal 2005 decreased 29 percent, from $9.0 billion in the prior year to $6.4 billion, as semiconductor manufacturers reduced their capital investments to align inventories with demand. Following the trend of decreasing orders during fiscal 2005, net sales decreased by 13 percent from $8.0 billion for fiscal 2004 to $7.0 billion for fiscal 2005, reflecting lower demand for semiconductor products.


New orders for fiscal 2006 increased 55 percent, from $6.4 billion in the prior year to $9.9 billion, as customer demand increased. Following the trend of increasing orders during fiscal 2006, net sales increased by 31 percent, from $7.0 billion for fiscal 2005 to $9.2 billion for fiscal 2006.

Gross Margin

Gross margin as a percentage of net sales decreased from 46.2 percent for fiscal 2004 to 44.1 percent for fiscal 2005, and increased to 46.8 percent for fiscal 2006. The higher gross margin percentage for fiscal 2004 was principally attributable to improved revenue levels, changes in product mix, decreased product costs, and increased manufacturing volume, resulting in higher absorption of manufacturing and field service costs and the completion of refocused product efforts. The higher gross margin in fiscal 2004 was partially offset by increased variable compensation costs as a result of improved operating performance. The decrease in gross margin from fiscal 2004 to fiscal 2005 was due to lower revenue levels, lower manufacturing absorption and changes in product mix, which were partially offset by initiatives for cost reduction and efficiency improvement, such as common platform architecture and parts, lower cost sourcing and cycle time reduction. The increase in the gross margin percentage from fiscal 2005 to fiscal 2006 was principally attributable to the combination of higher revenue levels, decreased product costs and increased manufacturing volume and absorption, partially offset by increased variable and equity-based compensation costs. Applied began recognizing expenses associated with stock options and the ESPP in fiscal 2006. Gross margin during fiscal 2006 included $37 million of equity-based compensation expense.

Research, Development and Engineering

Applied’s future operating results depend to a considerable extent on its ability to maintain a competitive advantage in the products and services it provides. Applied believes that it is critical to continue to make substantial investments in RD&E to assure the availability of innovative technology that meets the current and projected requirements of its customers’ most advanced designs. Applied has historically maintained its commitment to investing in RD&E in order to continue to offer new products and technologies. As a result, RD&E expenses were $992 million (12 percent of net sales) for fiscal 2004, $941 million (13 percent of net sales) for fiscal 2005, and $1.2 billion (13 percent of net sales) for fiscal 2006. Equity-based compensation expenses during fiscal 2006 associated with research, development and engineering functions totaled $76 million. Development cycles range from 12 to 36 months depending on whether the product is an enhancement of an existing product or a new product. Most of Applied’s existing products resulted from internal development activities and innovations involving new technologies, materials and processes. In certain instances, Applied acquires technologies, either in existing or new product areas, to complement its existing technology capabilities and to reduce time to market.

In fiscal 2004, Applied continued its investment in developing technologies for future generation manufacturing. Advances were made in several key areas, including technology for enhancing transistor and interconnect performance.

In fiscal 2005, Applied focused on developing systems for customers’ advanced chip designs, including systems to enable smaller and faster interconnect and transistor structures with 65nm, 45nm and below geometries and flat panel display systems to process larger glass substrates.

In fiscal 2006, Applied continued its development of systems to increase chip performance, especially for Flash and DRAM devices. Applied also focused on developing systems for 32nm and 22nm copper/low k interconnect processing technologies to address critical manufacturing challenges that chipmakers face as they transition to future device generations, helping them to bring new products to market more rapidly while minimizing risk. Applied also continued to focus on developing flat panel display systems to process even larger glass substrates.

During fiscal 2006, Applied recorded an in-process research and development (IPR&D) expense in the amount of $14 million related to the acquisition of Applied Films. Applied’s methodology for allocating the purchase price relating to purchased acquisitions to IPR&D was determined through established valuation techniques. The IPR&D was expensed upon acquisition because technological feasibility had not been established and no future alternative uses existed. No IPR&D charges were recorded in fiscal 2005. During fiscal 2004, Applied recorded an IPR&D expense in the amount of $6 million related to the acquisition of Torrex Equipment Corporation.


Marketing, Selling, General and Administrative

Marketing, selling, general and administrative expenses were $752 million (9 percent of net sales) for fiscal 2004, decreased to $697 million (10 percent of net sales) for fiscal 2005, and increased to $907 million (10 percent of net sales) for fiscal 2006. The decrease in operating expenses from fiscal 2004 to 2005 was due to lower business volume. Operating expenses were affected by reductions in variable compensation due to lower operating performance and focus on cost controls. The increase from fiscal 2005 to 2006 correlated to the increase in business volume, as well as increases in variable compensation as a result of improved operating performance, equity-based compensation expense, and spending on the Company’s business transformation initiative, partially offset by savings resulting from Applied’s continued focus on controlling its overall cost structure. Equity-based compensation expenses during fiscal 2006 associated with marketing, sales and general and administrative functions totaled $104 million. During fiscal 2006, Applied launched the planning stage of its multi-year business transformation initiative, which is expected to include the design of certain new company-wide business processes and the transition to a single-vendor software system to perform various functions, such as order management and manufacturing control.

Restructuring and Asset Impairments

Restructuring actions taken in fiscal 2004 were intended to better align Applied’s cost structure with prevailing market conditions due to the industry downturn at the time. These actions, which were necessary as a result of reduced business volume, reduced Applied’s global workforce and consolidated global facilities. Restructuring, asset impairments and other charges for fiscal 2004 totaled $167 million, consisting of $65 million for facility consolidations, $6 million for severance and benefits, and $96 million for other costs, primarily fixed asset writeoffs due to facility consolidations.

As of October 29, 2006, the fiscal 2004 restructuring actions were completed, and restructuring reserve balances consisted principally of remaining lease commitments associated with facilities.

During the first quarter of fiscal 2006, Applied’s Board of Directors approved a plan to disinvest a portion of Applied’s real estate and facilities portfolio (the Plan). Properties with an estimated fair value of $56 million were reported as assets held-for-sale and reclassified from property, plant and equipment on the Consolidated Balance Sheet. Applied recorded an asset impairment charge of $124 million during the first quarter of fiscal 2006 to write down the following properties to estimated fair value: (1) facilities in Narita, Japan; Chunan, Korea; Hillsboro, Oregon; Danvers, Massachusetts; and (2) 26 acres of unimproved land in Hillsboro, Oregon. As part of the Plan, Applied also recorded a charge in the amount of $91 million for future lease obligations that were scheduled to continue through fiscal 2014 related to the closure of its leased Hayward, California facility. During the third quarter of fiscal 2006, Applied sold the Danvers, Massachusetts facility for net proceeds of $16 million and recognized a gain of $4 million. During the fourth quarter of fiscal 2006, Applied recorded additional impairment charges on the Narita and Chunan facilities of $6 million and recorded a restructuring charge of $4 million related to environmental contamination of the Narita site. During the second, third and fourth quarters of fiscal 2006, Applied consumed $9 million in restructuring reserves related to the Hayward campus in rental and operating costs. In the fourth quarter of fiscal 2006, the Hayward lease obligation was terminated for $81 million. Applied continues to actively market the remaining properties.

For further details, see Note 6 of Notes to Consolidated Financial Statements.

Litigation Settlements, Net

Litigation settlements, net were $27 million for fiscal 2004 and consisted of costs of $28 million related to two separate patent litigation settlements, net of a gain of $1 million related to a legal settlement in favor of Applied. During fiscal 2005 and 2006, there were no material litigation settlements.

Net Interest Income

Net interest income was $66 million for fiscal 2004, $134 million for fiscal 2005 and $149 million for fiscal 2006. The increases in net interest income from fiscal 2004 to 2005 and from 2005 to 2006 were due primarily to a substantial increase in interest rates combined with a decrease in interest expense associated with scheduled debt maturities in September 2004 and September 2005.

During the fourth quarter of fiscal 2006, Applied repurchased 145 million shares of outstanding common stock for an aggregate purchase price of $2.5 billion under an accelerated buyback program. The repurchase was funded with Applied’s existing cash and investments. A portion of the investment portfolio was sold to fund the accelerated stock buyback, resulting in lower interest income due to the realization of losses associated with certain investments and a reduced investment portfolio.

Income Taxes

Applied’s effective income tax provision rate was 26.1 percent for fiscal 2004, 23.5 percent for fiscal 2005 and 30.0 percent for fiscal 2006. Applied’s effective rate of 23.5 percent for fiscal 2005 reflected the favorable resolution of audits of prior years’ income tax filings of $118 million and a change in estimate with respect to export tax benefits of $14 million, partially offset by a charge of $32 million relating to the distribution of foreign earnings under the American Jobs Creation Act of 2004 (the Jobs Creation Act). Applied’s effective tax rate of 30.0 percent for fiscal 2006 reflected benefits of $61 million principally related to the favorable resolution of audits of prior years’ income tax filings, partially offset by a $17 million charge from the expensing of equity-based compensation.

The Jobs Creation Act, enacted in fiscal 2004, provides for a three year phase-out of current extraterritorial income tax (ETI) benefits and replaces ETI with a phased-in nine percent domestic production activity deduction that will not be fully effective until 2010. The Jobs Creation Act will not fully replace Applied’s current ETI tax benefits.

Applied’s future effective income tax rate depends on various factors, such as tax legislation, the geographic composition of Applied’s pre-tax income, and non-tax deductible expenses incurred in connection with acquisitions. Management carefully monitors these factors and timely adjusts the effective income tax rate accordingly.

MANAGEMENT DISCUSSION FOR LATEST QUARTER

Overview

Applied provides nanomanufacturing technology tm solutions for the global semiconductor, liquid crystal display (LCD), solar and related industries, with a broad portfolio of innovative equipment, service and software products. Applied’s customers include manufacturers of semiconductor chips and wafers, LCDs, solar photovoltaic (PV) cells, flexible electronics and energy-efficient glass. Applied operates in four reportable segments: Silicon, Fab Solutions, Display, and Adjacent Technologies. Product development and manufacturing activities occur in North America, Europe, Israel and Asia. Applied’s broad range of equipment and service products are highly technical and are sold through a direct sales force.

As a supplier to the semiconductor and semiconductor-related industries, Applied’s results are driven by worldwide demand for integrated circuits, which in turn depends on end-user demand for electronic products. Applied’s business is subject to cyclical industry conditions as demand for manufacturing equipment and services can change depending on supply and demand for chips, LCD’s and other electronic devices as well as other factors, such as technological advances in fabrication processes.

Results for the first nine months of fiscal 2007 reflected improved conditions in the semiconductor industry that began with the industry’s recovery in 2006. During this period conditions in the display industry were mixed as manufacturers postponed capacity additions despite strong consumer demand. Orders and net sales increased during the first nine months of fiscal 2007 over the corresponding period in fiscal 2006, primarily due to strong demand from DRAM and flash memory chip manufacturers, partially offset by a significant decline in the LCD equipment business as manufacturers absorbed capacity following substantial growth in 2006. Orders declined for the third quarter of fiscal 2007 compared to the prior year period reflecting the weakness in demand for LCD equipment, in addition to a drop in demand for equipment from foundries and logic customers and lower fab operations demand. Sales increased slightly for the third quarter of fiscal 2007, compared to the third quarter of fiscal 2006, as strength in memory was offset by lower fab operations spending.

Net income for the first nine months of fiscal 2007 improved compared to the same period in the prior year due to higher sales and lower restructuring and asset impairment charges and a continued focus on operating efficiency and cost controls, offset in part by lower interest income. Fiscal 2007 results included restructuring and asset impairment and other charges associated with ceasing development of beamline implant products, equity-based compensation expenses, and an in-process research and development (IPR&D) expense associated with the acquisition of certain net assets of Brooks Automation, Inc. (Brooks Software). Net income for the third quarter of fiscal 2007 declined compared to the same period in the prior year due to lower interest income and losses recognized on the equity method investment, partially offset by savings from a continued focus on operating efficiency and cost controls.

Results of Operations

Applied received new orders of $2.3 billion for the third quarter of fiscal 2007, compared to $2.6 billion for the second quarter of fiscal 2007 and $2.7 billion for the third quarter of fiscal 2006. New orders for the third quarter of fiscal 2007 decreased by 14 percent from the preceding quarter and decreased by 14 percent from the third quarter of fiscal 2006. The decrease in new orders for the third quarter of fiscal 2007 from the previous quarter was primarily attributable to lower demand for semiconductor equipment for DRAM applications as customers absorbed recently-added capacity, compounded by lower demand for service products and continuing weakness in foundry and LCD equipment demand. New orders increased 4 percent to $7.5 billion for the first nine months of fiscal 2007, compared to $7.2 billion for the first nine months of fiscal 2006. Increased orders for the first nine months reflected increased demand for semiconductor manufacturing equipment and service products, partially offset by delays in investment by LCD customers.

Applied’s backlog for the most recent three fiscal quarters was as follows: $3.4 billion at July 29, 2007, $3.7 billion at April 29, 2007, and $3.6 billion at January 28, 2007. Backlog consists only of orders for which written authorizations have been accepted, shipment dates within 12 months have been assigned and revenue has not been recognized. Due to the potential for customer changes in delivery schedules or cancellation of orders, Applied’s backlog at any particular time is not necessarily indicative of actual sales for any future periods.

Net sales increased 1 percent to $2.6 billion for the third quarter of fiscal 2007, compared to $2.5 billion for the second quarter of fiscal 2007 and the third quarter of fiscal 2006, reflecting higher net sales of semiconductor equipment to memory application manufacturers, partially offset by continued delays in capital investment by LCD manufacturers and lower fab operations spending. Net sales increased 11 percent to $7.4 billion for the first nine months of fiscal 2007, compared to $6.6 billion for the first nine months of fiscal 2006, reflecting higher net sales of semiconductor equipment to memory application manufacturers, partially offset by continued delays in capital investment by LCD manufacturers.

Gross margin percentage was 47.5 percent for the third quarter of fiscal 2007, compared to 48.1 percent for the third quarter of fiscal 2006. The decrease in the gross margin percentage for the third quarter of fiscal 2007 from that of the prior year’s period was principally attributable to product mix, incremental charges attributable to acquisitions consisting of inventory fair value adjustments on products sold and amortization of purchased intangible assets, partially offset by higher revenue levels and lower material costs. Gross margin during the third quarters of fiscal 2006 and 2007 included $9 million and $8 million, respectively, of equity-based compensation expense.

Gross margin percentage was 46.4 percent for the for the first nine months of fiscal 2007, compared to 46.7 percent for the first nine months of fiscal 2006. The decrease in the gross margin percentage for the first nine months of fiscal 2007 from that of the prior year’s period was principally attributable to inventory-related charges of $53 million associated with ceasing development of beamline implant products, incremental charges attributable to acquisitions consisting of inventory fair value adjustments on products sold and amortization of purchased intangible assets and product mix, partially offset by higher revenue levels and lower material costs. Gross margin during the first nine months of fiscal 2006 and 2007 included $27 million and $22 million, respectively, of equity-based compensation expense.

Operating expenses included expenses related to RD&E, marketing and selling (M&S), and general and administrative (G&A). Expenses related to RD&E, M&S and G&A were $543 million for the third quarter of fiscal 2007 compared to $545 million for the third quarter of fiscal 2006, and $1.6 billion for the first nine months of fiscal 2007 compared to $1.5 billion for the first nine months of fiscal 2006. Higher operating expenses in these categories during the first nine months of fiscal 2007 compared to the same period in the prior year were principally attributable to increased operating costs from acquired businesses. These were partially offset by lower equity and variable compensation expenses and savings from cost control initiatives, including ceasing development of beamline implant products and transitioning to managed services providers to perform information technology and business infrastructure support. During the first nine months of fiscal 2007 and fiscal 2006, Applied recognized RD&E expenses for IPR&D charges related to acquisitions of $5 million and $14 million, respectively. (See Note 12 of the Notes to Consolidated Condensed Financial Statements.)

Operating expenses for the nine months ended July 29, 2007 include inventory-related charges reported as cost of products sold of $53 million, other operating expenses of $3 million and restructuring and asset impairment charges of $27 million associated with ceasing development of beamline implant products. (See Note 7 of Notes to Consolidated Condensed Financial Statements.)

Operating expenses during the first nine months of fiscal 2006 and 2007 included asset impairment and restructuring charges of $211 million, and a benefit of $4 million, respectively, related to the disinvestment of certain real estate. (See Note 7 of Notes to Consolidated Condensed Financial Statements.)

Net interest income was $22 million and $42 million for the three months ended July 29, 2007 and July 30, 2006, respectively and $67 million and $121 million for the nine months ended July 29, 2007 and July 30, 2006, respectively. Lower net interest income during the third quarter and first nine months of fiscal 2007 was primarily due to the reduction in cash and investments during the fourth quarter of fiscal 2006, when Applied repurchased 145 million shares of its outstanding common stock for an aggregate purchase price of $2.6 billion under an accelerated buyback program. The repurchase was funded with Applied’s existing cash and investments, resulting in lower interest income.

Applied’s effective income tax rate for the third quarter of fiscal 2007 was 31.1 percent. Applied’s effective income tax rate was 29.1 percent for the comparable quarter of fiscal 2006 and included benefits of $34 million due primarily to a favorable resolution of audits of prior years’ income tax filings. Applied’s future effective income tax rate depends on various factors, such as tax legislation, the geographic composition of Applied’s pre-tax income, and the tax rate on equity compensation. Management carefully monitors these factors and timely adjusts the effective income tax rate accordingly.

Segment Information

A description of the products and services, as well as financial data, for Applied’s Silicon, Fab Solutions, Display, and Adjacent Technologies reportable segments can be found in Note 14 of Notes to Consolidated Condensed Financial Statements. Future changes to Applied’s internal financial reporting structure may result in changes to the reportable segments disclosed. Applied does not allocate to its reportable segments certain operating expenses which are reported separately at the corporate level. These unallocated costs include charges for equity-based and certain components of variable compensation, corporate marketing and sales, corporate functions (certain management, finance, legal, human resources and RD&E), unabsorbed information technology and occupancy. Prior to the fourth quarter of fiscal 2006, Applied operated in one reportable segment. Accordingly, prior period amounts have been reclassified to conform to the current presentation. Discussions below include the results of each reportable segment for the three and nine months ended July 30, 2006 and July 29, 2007.

Silicon Segment

The Silicon segment includes semiconductor capital equipment for etch, front end, thin film, chemical mechanical planarization (CMP), and inspection. Development efforts are focused on solving customers’ key technical challenges, including transistor performance and nanoscale patterning, and on reducing chip manufacturing costs. A significant portion of fiscal 2007 demand was attributable to a growing market for consumer products with increased memory content.

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