The Daily Magic Formula Stock for 05/05/2008 is FormFactor Inc. According to the Magic Formula Investing Web Site, the ebit yield is 28% and the EBIT ROIC is 50-75 %.
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We design, develop, manufacture, sell and support, precision high performance advanced semiconductor wafer probe cards. Semiconductor manufacturers use our wafer probe cards to perform wafer sort and test on the semiconductor die, or chips, on the whole semiconductor wafer prior to singulation of the wafer into individual chips. During wafer sort and test, a wafer probe card is mounted in a prober, which in turn is connected to a semiconductor tester. The wafer probe card is used as an interface to connect electronically with and test individual chips on a wafer. Our wafer probe cards are used by our customers in the front end of the semiconductor manufacturing process, as are our parametric or in-line probe cards. We introduced our first wafer probe card based on our MicroSpringÂ® interconnect technology in 1995. We offer products and solutions that are custom designed for semiconductor manufacturers' unique wafer designs and enable them to reduce their overall cost of test.
In fiscal 2007, we benefited from semiconductor manufacturers' strong demand for our advanced wafer test products as global semiconductor device production increased. Overall, our revenue grew for our products that address the dynamic random access memory, or DRAM, market, driven primarily by the continued ramp of 70 nanometer technology nodes at our DRAM customers, as well as our customers' transition to one gigabit DDR2 devices. Additionally, applications such as mobile RAM and graphic RAM contributed to our DRAM revenue growth. Strong demand from existing customers fueled both NOR and NAND flash growth. For Known Good Die, or KGD, devices, we saw higher adoption of our high-frequency test at probe product, or HFTAP, largely driven by the demand for mobile devices, such as NOR, specialty NAND, mobile RAM and PSRAM for at-speed testing. Demand for our wafer level burn-in products grew as customers moved more burn-in of their devices to the wafer level. Revenues for our products that address the logic market grew as a result of the new technology node transition for area array flip-chip microprocessor products and the introduction of our new probe cards for higher parallelism probing of wire bond devices.
Our products are based on our proprietary technologies, including our MicroSpring interconnect technology and design tools. Our MicroSpring interconnect technology, which includes resilient spring-like contact elements, enables us to produce wafer probe cards for applications that require reliability, speed, precision and signal integrity. We manufacture our MicroSpring contact elements through precision micro-machining and scalable semiconductor-like wafer fabrication processes. Our MicroSpring contacts are springs that optimize the relative amounts of force on, and across, a bond pad during the test process and maintain their shape and position over a range of compression. These characteristics allow us to achieve reliable, electrical contact on either clean or oxidized surfaces, including bond pads on a wafer. MicroSpring contacts enable our wafer probe cards to make hundreds of thousands of touchdowns with minimal maintenance for many device applications. The MicroSpring contact can be attached to many surfaces, or substrates, including printed circuit boards, silicon wafers, ceramics and various metalized surfaces.
Since its original conception, the MicroSpring contact has evolved into a library of spring shapes and technologies. Our designers use this library to design an optimized custom wafer probe card for each customer-unique application. Since developing this fundamental technology, we have broadened and refined it to respond to the increasing requirements of testing smaller, faster and more complex semiconductor devices. We continue to invest in research and development activities around our interconnect technologies, including our micro-electro-mechanical systems, or MEMS, technology, as our MicroSpring contacts have scaled in size with the evolution of semiconductors.
Our MicroSpring contacts include geometrically precise tip structures. These tip structures are the parts of our wafer probe cards that come into physical contact with the devices being tested, and are manufactured using proprietary micro-machining semiconductor-like processes. These tip structures enable precise contact with small bond pad sizes and pitches. Our technology allows for the design of specific geometries of the contact tip that deliver precise and predictable electrical contact for a customer's particular application.
Our wafer probe cards are custom products that are designed to order for our customers' unique wafer designs. For high parallelism memory test applications, our products require large area contact array sizes because they must accommodate tens of thousands of simultaneous contacts. Our current technology enables probe cards for certain applications to be populated with over 40,000 contacts. This requirement poses fundamental challenges that our technology addresses, including the planarity of the array, the force needed to make contact and the need to touch all bond pads with equal accuracy. We have developed wafer probe cards that use array sizes ranging from 50 mm Ă— 50 mm up to array sizes suitable for contacting all die on a 300 mm wafer simultaneously, in combination with complex multi-layer printed circuit boards that we have designed.
We have invested and intend to continue to invest considerable resources in our wafer probe card design tools and processes. These tools and processes enable automated routing and trace length adjustment within our printed circuit boards and greatly enhance our ability to rapidly design and lay out complex printed circuit board structures. Our proprietary design tools also enable us to design wafer probe cards particularly suited for testing today's low voltage, high power chips. Low voltage, high frequency chips require superior power supply performance. Our MicroSpring interconnect technology is used to provide a very low inductance, low resistance electrical path between the power source and the chip under test.
In 2007, we achieved a number of milestones, including the introduction of our TrueScale probe cards for testing wire bond logic and system-on-chip devices for mobile consumer and automotive applications, and the delivery of our first 300 mm, one touchdown wafer-level burn-in probe cards incorporating our proprietary "Harmony" architecture for testing DRAM devices, which is capable of contacting approximately 40,000 test pads in one touchdown. TrueScale, which offers scalability down to a 40 micron pad pitch, addresses the limitations of conventional probing technology that cannot scale below 50 micron pad pitch at high parallelism. TrueScale is designed to increase semiconductor manufacturers' throughput and lower test costs, while supporting their technology roadmap for smaller pad pitches. Our Harmony architecture addresses some of the significant challenges presented by the future demands of single touchdown wafer probing and very high parallelism wafer test. We believe it will be a key building block for our future generations of large area array flash, DRAM, wafer level burn-in and high frequency probing solutions.
Because our customers typically use our wafer probe cards in a wide range of operating temperatures, as opposed to conducting wafer probe test at one predetermined temperature, we have designed complex thermal compensation characteristics into our products. We select our wafer probe card materials after careful consideration of the potential range of test operating temperatures and design our wafer probe cards to provide for a precise match with the thermal expansion characteristics of the wafer under test. As a result, our wafer probe cards generally are able to accurately probe over a large range of operating temperatures. This feature enables our customers to use the same wafer probe card for both low and high temperature testing without a loss of performance. In addition, for those testing situations that require positional accuracy at a specific temperature, we have designed wafer probe cards optimized for testing at such temperatures.
Our many spring shapes, different geometrically-precise tip structures, various array sizes and diverse printed circuit board layouts enable a wide variety of solutions for our customers. Our designers select the most appropriate of these elements, or modify or improve upon such existing elements, and integrate them with our other technologies to deliver a custom solution optimized for the customer's requirements.
Our customers include manufacturers in the DRAM, flash and logic markets. Our customers use our wafer probe cards to test DRAM chips including DDR, DDR2, DDR3, SDRAM, PSRAM, mobile DRAM, and Graphic DRAM, NOR and NAND flash memory chips, serial data devices, chipsets, microprocessors and microcontrollers.
Information concerning revenue by geographic region and by country based upon invoicing location appears under "Item 7: Management's Discussion and Analysis of Financial Condition and Results of Operationsâ€”Revenuesâ€”Reven ue by Geographic Region" and Note 10 (Operating Segment and Geographic Information) to our consolidated financial statements, which are included elsewhere in this 10-K.
Our backlog was $46.8 million at December 29, 2007 compared to $47.4 million at December 30, 2006. We manufacture our wafer probe cards based on order backlog and customer commitments. In addition, due to our customers' short delivery time requirements, we at times produce our products in anticipation of demand for our products. Backlog includes only orders for which written authorizations have been accepted, shipment dates within 12 months have been assigned and, or shipment has occurred but revenue has not been recognized. In addition, backlog includes service revenue for existing product service agreements to be earned within the next 12 months. Customers may delay delivery of products or cancel orders prior to shipment, subject to possible cancellation penalties. Due to possible changes in delivery schedules and cancellations of orders, our backlog on any particular date is not necessarily indicative of actual sales for any succeeding period. Delays in delivery schedules and/or a reduction in backlog during any particular period could have a material adverse effect on our business and results of operations.
Our wafer probe cards are custom products that we design to order for our customers' unique wafer designs. We manufacture our products at our new facility located in Livermore, California. We completed the transition to our new manufacturing facility in fiscal 2006. We also continued utilizing our old facility, which is also located in Livermore, for additional manufacturing functions. In the fourth quarter of fiscal 2007 we discontinued all manufacturing functions at our old facility. We have initiated the first phase of our company's current global manufacturing plan to establish a new manufacturing facility in Singapore. Our current plan, portions of which we have delayed and are further evaluating, is to first expand our assembly and test and back-end manufacturing processes in Singapore, and then expand our manufacturing capabilities in Singapore to include our front-end manufacturing processes.
Our proprietary manufacturing processes include wirebonding, photolithography, plating and metallurgical processes, dry and electro-deposition, and complex interconnection system design. The critical steps in our manufacturing process are performed in a Class 100 clean room environment. We also expend considerable resources on the assembly and test of our wafer probe cards and on quality control.
We depend upon suppliers for some critical components of our manufacturing processes, including ceramic substrates and complex printed circuit boards, and for materials used in our manufacturing processes. Some of these components and materials are supplied by a single vendor. Generally, we rely on purchase orders rather than long-term contracts with our suppliers, which subjects us to risks including price increases and component shortages. We continue to evaluate alternative sources of supply for these components and for materials.
We maintain a repair and service capability in Livermore, California. We also provide repair and service capabilities in our service centers in Gyeonggi-do, South Korea; Dresden, Germany; Yokohama City, Japan and Jubei City, Taiwan.
Research, Development and Engineering
The semiconductor industry is subject to rapid technological change and new product introductions and enhancements. We believe that our continued commitment to research and development and our timely introduction of new and enhanced wafer probe test solutions and other technologies related to our MicroSpring interconnect technology are integral to maintaining our competitive position. We continue to invest considerable time and resources in creating structured processes for undertaking, tracking and completing our development projects, and plan to implement those developments into new product or technology offerings. We continue to allocate significant resources to these efforts and to use automation and information technology to provide additional efficiencies in our research and development activities.
We have historically devoted approximately 11% to 14% of our revenues to research and development programs. Research and development expenses were $61.0 million for fiscal 2007, $46.6 million for fiscal 2006, and $28.3 million for fiscal 2005.
Our research and development activities, including our product engineering activities, are directed by individuals with significant expertise and industry experience. As of December 29, 2007, we had 218 employees in research and development.
Sales and Marketing
We sell our products utilizing a proprietary sales model that emphasizes the customer's total cost of ownership as it relates to the costs of test. With this sales model, we strive to demonstrate how test costs can be reduced by simulating the customer's test floor environment, including testers and probers, utilizing our products and comparing the overall cost of test to that of conventional wafer probe cards.
We sell our products worldwide primarily through our direct sales force, a distributor and one independent sales representative. As of December 29, 2007, we had 21 sales professionals. In North America, South Korea, Taiwan and Japan we sell our products through our direct sales force. In Europe, our local sales team works with one independent sales representative. In China, Malaysia, Philippines and Singapore, we sell through Spirox Corporation, our regional distributor. We also have the ability to sell our products direct to customers in these regions. In October 2005, we terminated our agreement with Spirox for the distribution of our products in Taiwan and transitioned to a direct sales model.
Our marketing staff, located in Livermore, California, Jubei City, Taiwan and Tokyo, Japan, works closely with customers to understand their businesses, anticipate trends and define products that will provide significant technical and economic advantages to our customers.
We utilize a highly skilled team of field application engineers that support our customers as they integrate our products into their manufacturing processes. Through these customer relationships, we develop a close understanding of customer and product requirements, thereby accelerating our customers' production ramps.
We are subject to U.S. federal, state and local, and foreign governmental laws and regulations relating to the protection of the environment, including those governing the discharge of pollutants into the air and water, the management and disposal of hazardous substances and wastes, the clean-up of contaminated sites and the maintenance of a safe workplace. We believe that we comply in all material respects with the environmental laws and regulations that apply to us, including those of the California Department of Toxic Substances Control, the Bay Area Air Quality Management District, the City of Livermore Water Resources Division and the California Division of Occupational Safety and Health. In fiscal 2007, we received two notices of violation from the City of Livermore regarding violation of certain applicable waste water discharge limits. For each notice received, we promptly investigated the violation, took appropriate steps to address the cause of the violation and implemented corrective measures to prevent a recurrence. We have also implemented additional waste water treatment capability in consultation with the City of Livermore. In addition, we are discussing with the City of Livermore the purchase of additional waste water discharge capacity, which we require as a result of our increased manufacturing capacity.
While we believe that we are in compliance in all material respects with the environmental laws and regulations that apply to us, in the future, we may receive additional environmental violation notices, and if received, final resolution of the violations identified by these notices could harm our operations, which may adversely impact our operating results and cash flows. New laws and regulations, stricter enforcement of existing laws and regulations, the discovery of previously unknown contamination at our or others' sites or the imposition of new cleanup requirements could also harm our operations, thereby adversely impacting our operating results and cash flows.
The highly competitive wafer probe card market is comprised of many domestic and foreign companies, and has historically been fragmented with many local suppliers servicing individual customers. Our current and potential competitors in the wafer probe card market include Advantest Corporation, AMST Co., Ltd., Cascade Microtech, Inc., Feinmetall GmbH, Korea Instrument Co., Ltd., Japan Electronic Materials Corporation, SV Probe, Inc., Micronics Japan Co., Ltd., Microfriend Inc., Technoprobe Asia Pte. Ltd., MicroProbe, Inc., Phicom Corporation, Tokyo Cathode Laboratory Co., Ltd., Tokyo Electron Ltd., Touchdown Technologies, Inc., TSE Co., Ltd. and Wentworth Laboratories, Inc., among others. In addition to the ability to address wafer probe card performance issues, the primary competitive factors in the industry in which we compete include product quality and reliability, price, total cost of ownership, lead times, the ability to provide prompt and effective customer service, field applications support and timeliness of delivery.
Some of our competitors are also suppliers of other types of test equipment or other semiconductor equipment, or offer both advanced wafer probe cards and needle probe cards, and may have greater financial and other resources than we do. We expect that our competitors will enhance their current wafer probe products and that they may introduce new products that will be competitive with our wafer probe cards. In addition, it is possible that new competitors, including test equipment manufacturers, may offer new technologies that reduce the value of our wafer probe cards.
Additionally, semiconductor manufacturers may implement chip designs that include built-in self-test capabilities or similar functions or methodologies that increase test throughput and eliminate some or all of our current competitive advantages. Our ability to compete favorably is also adversely affected by (1) low volume orders that do not meet our present minimum volume requirements, (2) very short cycle time requirements which may be difficult for us to meet, (3) long-standing relationships between our competitors and certain semiconductor manufacturers, and (4) semiconductor manufacturer test strategies that include low performance semiconductor testers.
Our success depends in part upon our ability to continue to innovate and invest in research and development to meet the semiconductor testing requirements of our customers, to maintain and protect our proprietary technology and to conduct our business without infringing the proprietary rights of others. We rely on a combination of patents, trade secrets, trademarks and contractual restrictions on disclosure to protect our intellectual property rights.
As of December 29, 2007, we had 471 issued patents, of which 252 are United States patents and 219 are foreign patents. The expiration dates of these patents range from 2013 to 2026. Our issued patents cover many of the features of our MicroSpring interconnect technology, as well as some of our inventions related to wafer probe cards and testing, wafer-level packaging and test, sockets and assemblies and chips. In addition, as of December 29, 2007, we had 557 patent applications pending worldwide, including 148 United States applications, 377 foreign national or regional stage applications and 32 Patent Cooperation Treaty applications. We cannot provide any assurance that our current patent applications, or any future patent applications that we may file, will result in a patent being issued with the scope of the claims we seek, or at all, or whether any patents that we may obtain will not be challenged or invalidated. Even if additional patents are issued, our patents might not provide sufficiently broad coverage to protect our proprietary rights or to avoid a third party claim against one or more of our products or technologies.
We have both registered and unregistered trademarks, including FormFactor, Harmony, MicroSpring, MicroForce, MicroLign, TRE, TrueScale and the FormFactor logo.
We routinely require our employees, customers, suppliers and potential business partners to enter into confidentiality and non-disclosure agreements before we disclose to them any sensitive or proprietary information regarding our products, technology or business plans. We require our employees to assign to us proprietary information, inventions and other intellectual property they create, modify or improve.
Legal protections afford only limited protection for our proprietary rights. We also may not be successful in our efforts to enforce our proprietary rights. Notwithstanding our efforts to protect our proprietary rights, unauthorized parties may attempt to copy aspects of our products or to obtain and use information that we regard as proprietary. From time to time, we have become aware of situations where others are or may be infringing on our proprietary rights. We evaluate these situations as they arise and elect to take actions against these companies as we deem appropriate. Others might independently develop similar or competing technologies or methods or design around our patents, or attempt to manufacture and sell infringing products in countries that do not strongly enforce intellectual property rights or hold invalid our intellectual property rights. In addition, leading companies in the semiconductor industry have extensive patent portfolios and other intellectual property with respect to semiconductor technology. In the future, we might receive claims that we are infringing intellectual property rights of others or that our patents or other intellectual property rights are invalid. We have received in the past, and may receive in the future, communications from third parties inquiring about our interest in licensing certain of their intellectual property or more generally identifying intellectual property that may be of interest to us.
We have invested significant time and resources in our technology and as a part of our ongoing efforts to protect the intellectual property embodied in our proprietary technologies, including our MicroSpring interconnect technology and design processes, we may pursue actions to enforce our intellectual property rights against infringing third parties.
For a description of the material patent-related proceedings in which we are involved, see "Item 3: Legal Proceedings".
As of December 29, 2007, we had 1,124 regular full-time employees, including 218 in research and development, 134 in sales and marketing, 124 in general and administrative functions, and 648 in operations. By region, 986 of our employees were in North America, 54 in Japan, 24 in Taiwan, 23 in South Korea, 23 in Singapore, and 14 in Europe. On February 5, 2008, we announced a cost reduction plan that will include reducing our global workforce by approximately 14%. The plan is designed to restructure our company to better align with the market environment.
No employees are currently covered by a collective bargaining agreement. We believe that our relations with our employees are good.
Dr. Homa Bahrami has served as a Director since December 2004. Dr. Bahrami is a Senior Lecturer at the Haas School of Business, University of California at Berkeley. Dr. Bahrami has been on the Haas School faculty since 1986 and is widely published on organizational design and organizational development challenges and trends in the high technology sector. Dr. Bahrami currently serves on the board of directors of one privately held company. Dr. Bahrami holds a Ph.D. in organizational behavior from Aston University, United Kingdom.
Dr. Thomas J. Campbell has served as a Director since January 2006. Dr. Campbell previously served as a Director from July 2003 through November 2004, when he resigned to become the Director of Finance for the State of California. Dr. Campbell was the California Director of Finance from December 2004 through November 2005. Dr. Campbell has served as the Dean of the Haas School of Business at the University of California at Berkeley since August 2002, taking a leave of absence from this post when he became California Director of Finance. Dr. Campbell was a professor at Stanford Law School from 1983 to August 2002. Dr. Campbell served as a U.S. congressman from 1989 to 1993 and from 1995 to January 2001, and as a California state senator from 1993 to 1995. Dr. Campbell also served as Director of the Federal Trade Commission's Bureau of Competition from 1981 to 1983. Dr. Campbell serves on the board of directors of Visa Inc., a publicly traded company, where he is Chairman of the Governance Committee and a member of the Compensation Committee. Dr. Campbell holds a B.A., an M.A. and a Ph.D. in economics from the University of Chicago, and a J.D. from Harvard Law School.
G. Carl Everett, Jr. has served as a Director since June 2001. Mr. Everett founded GCE Ventures, a venture advisement firm, in April 2001. Mr. Everett is also a partner at Accel LLP, a venture capital firm. From February 1998 to April 2001, Mr. Everett served as Senior Vice President, Personal Systems Group of Dell Inc. During 1997, Mr. Everett was on a personal sabbatical. From 1978 to December 1996, Mr. Everett held several management positions with Intel Corporation, including Senior Vice President and General Manager of the Microprocessor Products Group, and Senior Vice President and General Manager of the Desktop Products Group. Mr. Everett currently serves on the board of directors of three privately held companies. Mr. Everett holds a B.A. in business administration and a Doctorate of laws from New Mexico State University.
Dr. Igor Y. Khandros founded FormFactor in April 1993. Dr. Khandros has served as our Chief Executive Officer as well as a Director since that time. Dr. Khandros also served as our President from April 1993 to November 2004. From 1990 to 1992, Dr. Khandros served as the Vice President of Development of Tessera Technologies, Inc., a provider of chip scale packaging technology that he co-founded. From 1986 to 1990, he was employed at the Yorktown Research Center of IBM Corporation as a member of the technical staff and a manager. From 1979 to 1985, Dr. Khandros was employed at ABEX Corporation, a casting foundry and composite parts producer, as a research metallurgist and a manager, and he was an engineer from 1977 to 1978 at the Institute of Casting Research in Kiev, Ukraine. Dr. Khandros holds an M.S. equivalent degree in metallurgical engineering from Kiev Polytechnic Institute in Kiev, Ukraine, and a Ph.D. in metallurgy from Stevens Institute of Technology.
Lothar Maier has served as a Director since November 2006. Mr. Maier has served as the Chief Executive Officer and a member of the board of directors of Linear Technology Corporation, a supplier of high performance analog integrated circuits, since January 2005. Prior to that, Mr. Maier served as Linear Technology's Chief Operating Officer from April 1999 to December 2004. Before joining Linear Technology, Mr. Maier held various management positions at Cypress Semiconductor Corporation, a provider of high-performance, mixed-signal, programmable solutions, from 1983 to 1999, most recently as Senior Vice President and Executive Vice President of Worldwide Operations. Mr. Maier holds a B.S. in chemical engineering from the University of California at Berkeley.
James A. Prestridge has served as Chairman of our Board of Directors since August 2005, and as a Director since April 2002. Mr. Prestridge served as a consultant for Empirix Inc., a provider of test and monitoring solutions for communications applications, from October 2001 until October 2003. From June 1997 to January 2001, Mr. Prestridge served as a Director of five private companies that were amalgamated into Empirix. Mr. Prestridge served as a director of Teradyne, Inc., a manufacturer of automated test equipment, from 1992 until 2000. Mr. Prestridge was Vice-Chairman of Teradyne from January 1996 until May 2000 and served as Executive Vice President of Teradyne from 1992 until May 1997. Mr. Prestridge currently serves on the board of directors of one privately held company. Mr. Prestridge holds a B.S. in general engineering from the U.S. Naval Academy and an M.B.A. from Harvard University. Mr. Prestridge served as a Captain in the U.S. Marine Corps.
Dr. Mario Ruscev has served as our President and Director since joining our company in January 2008. Dr. Ruscev served from April 2006 to December 2007 as President of Testing Schlumberger Oilfield Services of Schlumberger Limited, a services company supplying technology, project management and information solutions for optimizing performance in the oil and gas industry. He also held several other executive positions at Schlumberger during his 23 year career with that company, including President of Schlumberger Water and Carbon Services from April 2002 to March 2006, President of Wireline Schlumberger Oilfield Services from January 2001 to March 2002 and President of Geco-Prakla Schlumberger Oilfield Services from April 1999 to December 2000. Dr. Ruscev received a Doctorate in nuclear physics from UniversitĂ©, Pierre et Marie Curie in Paris, France and a Ph.D. in nuclear physics from Yale University.
Harvey A. Wagner has served as a Director since February 2005. Mr. Wagner joined Caregiver Services, Inc., a provider of in-home care services, as the President and Chief Executive Officer and a member of the board of directors on April 7, 2008. Mr. Wagner founded the H.A. Wagner Group, LLC, a consulting firm, where he has served as managing principal since July 2007. Mr. Wagner previously served as President and Chief Executive Officer of Quovadx, Inc. (now Healthvision, Inc.), a software and services company, from October 2004 to July 2007, and as a member of the board of directors of Quovadx from April 2004 to July 2007. From May 2004 through October 2004, Mr. Wagner served as acting President and Chief Executive Officer of Quovadx. Prior to joining Quovadx, he served as Executive Vice President and Chief Financial Officer of Mirant Corporation, an independent energy company, from January 2003 through April 2004. In July 2003, Mirant filed a voluntary petition for relief under Chapter 11 of the U.S. Bankruptcy Code and exited Chapter 11 in January 2006. Prior to joining Mirant, Mr. Wagner was Executive Vice President of Finance, Secretary, Treasurer, and Chief Financial Officer at Optio Software, Inc., a provider of business process improvement solutions, from February 2002 to December 2002. From May 2001 to January 2002, he performed independent consulting services for various corporations. He was Chief Financial Officer and Chief Operating Officer for PaySys International, Inc. from December 1999 to April 2001. Mr. Wagner also serves on the board of directors of Cree, Inc., a publicly traded company, where he is Chairman of the Audit Committee and a member of the Nominating and Governance Committee. Mr. Wagner holds a B.B.A. in accounting from the University of Miami.
MANAGEMENT DISCUSSION FROM LATEST 10K
We design, develop, manufacture, sell and support precision, high performance advanced semiconductor wafer probe cards. Semiconductor manufacturers use our wafer probe cards to perform wafer sort and test on the semiconductor die, or chips, on the whole semiconductor wafer, prior to singulation of the wafer into individual chips. During wafer sort and test, a wafer probe card is mounted in a prober, which is in turn connected to a semiconductor tester, and the wafer probe card is used as an interface to connect electronically with and test individual chips on a wafer. Our wafer probe cards are used by our customers in the front end of the semiconductor manufacturing process, as are our parametric or in-line probe cards. We work closely with our customers to design, develop and manufacture custom wafer probe cards. Each wafer probe card is a custom product that is specific to the chip and wafer designs of the customer. At the core of our product offering are our proprietary technologies, including our MicroSpring interconnect technology and design processes. Our MicroSpring interconnect technology includes a resilient contact element manufactured at our production facilities in Livermore, California. We operate in a single industry segment and have derived substantially all of our revenues from the sale of wafer probe cards incorporating our MicroSpring interconnect technology.
We were formed in 1993 and in 1995 introduced our first commercial product. During 1996, we introduced the industry's first memory wafer probe card capable of testing up to 32 devices in parallel. In fiscal 2007, we achieved a number of product milestones, including the introduction of our TrueScale probe cards for testing wire bond logic and system-on-chip devices for mobile consumer and automotive applications, and the delivery of our first 300 mm, one touchdown wafer-level burn-in probe cards incorporating our Harmony architecture for testing DRAM devices. We also made progress toward achieving efficient volume production for our Harmony architecture-based products, reduced lead times and delivered certain Harmony-based products for testing DRAM devices to some of our customers, which are being used in commercial volume. Our revenues increased from $1.1 million in fiscal 1995 to $462.2 million in fiscal 2007.
In fiscal 2007, we benefited from semiconductor manufacturers' strong demand for our advanced wafer test products as global semiconductor device production increased. Overall, our revenue grew for our products that address the DRAM market, driven primarily by the continued ramp of 70 nanometer technology nodes at our DRAM customers, as well as our customers' transition to one gigabit DDR2 devices. Additionally, applications such as mobile RAM and graphic RAM contributed to our DRAM revenue growth. Strong demand from existing customers fueled both NOR and NAND flash growth. For KGD devices, we saw higher adoption of our HFTAP product largely driven by the demand for mobile devices, such as NOR, specialty NAND, mobile RAM and PSRAM for at-speed testing. Demand for our wafer level burn-in products grew as customers moved more burn-in of their devices to the wafer level. Revenues for our products that address the logic market grew as a result of the new technology node transition for area array flip-chip microprocessor products and the introduction of our new probe cards for higher parallelism probing of wire bond devices.
Our customers operate in the highly cyclical semiconductor industry and are subject to significant fluctuations in the demand for their products. Because of the nature of our customers and our business, our revenue growth is driven in significant part by the number of new semiconductor designs that our customers develop the technology transitions involved in these designs and our customers' production volumes. In the past, this has resulted in our being subject to demand fluctuations that have resulted in significant variations of revenues, expenses and results of operations in the periods presented. We expect these fluctuations and the resulting variations in our financial results, to continue in future periods.
We completed fiscal 2007 with fourth quarter revenues decreasing 4% to $120.5 million when compared to the third quarter of fiscal 2007. The slower fourth quarter was largely due to deteriorating semiconductor market conditions, particularly in the DRAM market. We expect the deteriorating market conditions for our semiconductor customers to continue in fiscal 2008 with, for example, DRAM semiconductor revenue declining significantly due to the protracted oversupply, and some of our DRAM customers delaying probe card purchases. In addition, while we have successfully qualified and delivered certain Harmony architecture-based wafer probe cards that are being used by some of our customers in commercial volume for testing semiconductor devices and reduced manufacturing lead times, we are continuing to experience the effects of the new product execution challenges for our Harmony-based products that we experienced in fiscal 2007, which have contributed to a more difficult competitive environment. To better align our company with the market environment, we announced on February 5, 2008 our commitment to implement a cost reduction plan that will include reducing our global workforce by approximately 14%.
The majority of our sales are directly to semiconductor manufacturers. In fiscal 2007, sales to four customers accounted for 63.0% of our revenues. Because the semiconductor industry is a relatively concentrated industry, we believe that sales to a limited number of customers will continue to account for a substantial part of our business. We generally have limited backlog and therefore we rely upon orders that are booked and shipped in the same quarter for about half of our revenues. Our backlog was $46.8million and $47.4 million at December 29, 2007 and December 30, 2006, respectively. We manufacture our wafer probe cards based on order backlog and customer commitments. In addition, due to our customers' short delivery time requirements, we at times produce our products in anticipation of demand for our products. Backlog includes only orders for which written authorizations have been accepted, shipment dates within 12 months have been assigned and revenue has not been recognized. In addition, backlog includes service revenue for existing product service agreements to be earned within the next 12 months. In addition to direct sales we also had sales to our distributor in prior years. Sales to our distributor were 1.0%, 1.6%and 23.0% of our revenues in fiscal 2007, 2006, and 2005, respectively. Currently, we have one distributor, Spirox Corporation, which serves Singapore, Philippines, Malaysia and the People's Republic of China. We also have the ability to sell our products directly to customers in these regions. Prior to October 2005, we sold our products in Taiwan through Spirox. In October 2005, we transitioned to a direct sales and service model in Taiwan.
Management focuses on various external measures that impact our performance, including for example, semiconductor manufacturer technology transitions, semiconductor manufacturing wafer fabrication facility expansions, semiconductor device architecture changes and implementations, and new market developments.
We believe the following information is key to understanding our business, our financial statements and the remainder of this discussion and analysis of our financial condition and results of operations:
Fiscal Year. Fiscal years ended December 29, 2007 and December 30, 2006 had 52 weeks each. The fiscal year ended December 31, 2005 had 53 weeks. Our fiscal year ends on the last Saturday in December.
Revenues. We derive substantially all of our revenues from product sales of wafer probe cards. Increases in revenues have resulted from increased demand for our existing products, the introduction of new, more complex products and the penetration of new markets. Revenues from our customers are subject to quarterly, annual and other fluctuations due to design cycles, technology adoption rates and cyclicality of the different end markets into which our customers' products are sold. We expect that revenues from the sale of wafer probe cards will continue to account for substantially all of our revenues for the foreseeable future.
Cost of Revenues. Cost of revenues consists primarily of manufacturing materials, payroll and manufacturing-related overhead. In addition, cost of revenues also includes costs related to the start up of our new manufacturing facility, which was completed in early 2006 and costs of the expansion of our manufacturing facility which was completed in 2007. Our manufacturing operations rely upon a limited number of suppliers to provide key components and materials for our products, some of which are a sole source. We order materials and supplies based on backlog and forecasted customer orders. Tooling and setup costs related to changing manufacturing lots at our suppliers are also included in the cost of revenues. We expense all warranty costs and inventory provisions or write-offs of inventory as cost of revenues.
We design, manufacture and sell a fully custom product into the semiconductor test market, which is subject to significant variability and demand fluctuations. Our wafer probe cards are complex products that are custom to a specific chip design and must be delivered on relatively short lead-times as compared to our overall manufacturing process. As our advanced wafer probe cards are manufactured in low volumes and must be delivered on relatively short lead-times, it is not uncommon for us to acquire production materials and start certain production activities based on estimated production yields and forecasted demand prior to or in excess of actual demand for our wafer probe cards. We record an adjustment to our inventory valuation for estimated obsolete and non-saleable inventories equal to the difference between the cost of inventories and the estimated market value based upon assumptions about future demand and market conditions. If actual market conditions are less favorable than those projected by management, additional inventory write down would be required. Once established, the original cost of our inventory less the related inventory valuation adjustments represents the new cost basis of such products. Reversal of these write downs is recognized only when the related inventory has been scrapped or sold.
Research and Development. Research and development expenses include expenses related to product development, engineering and material costs. Almost all research and development costs are expensed as incurred. We plan to continue to invest a significant amount in research and development activities to develop new technologies for current and new markets and new applications in the future. We expect these expenses to scale with revenue growth.
Selling, General and Administrative. Selling, general and administrative expenses include expenses related to sales, marketing, and administrative personnel, internal and outside sales representatives' commissions, market research and consulting, and other sales, marketing, and administrative activities. These expenses also include costs for enforcing our patent rights and regulatory compliance costs. We expect that selling expenses will increase as revenues increase and we expect that general and administrative expenses will increase in absolute dollars to support future revenue growth.
Critical Accounting Policies and Estimates
Our discussion and analysis of our financial condition and results of operations are based upon our consolidated financial statements, which have been prepared in accordance with U.S. generally accepted accounting principles. The preparation of these financial statements and related disclosures requires us to make estimates and assumptions that affect the reported amounts of assets and liabilities at the date of the financial statements and the reported amounts of net revenue and expenses in the reporting period. We regularly evaluate our estimates and assumptions related to allowances for doubtful receivables, inventories, marketable securities, income taxes, warranty obligations, contingencies, litigation and accrual for other liabilities. We base our estimates and assumptions on current facts, historical experience and various other factors that we believe to be reasonable under the circumstances, the results of which form the basis for making judgments about the carrying values of assets and liabilities and the accrual of costs and expenses that are not readily apparent from other sources. The actual results experienced by us may differ materially and adversely from our estimates. To the extent there are material differences between our estimates and the actual results, our future results of operations will be affected.
We believe that the following are critical accounting policies:
Revenue Recognition We recognize revenue when title and risk of loss have passed to the customer, there is persuasive evidence of an arrangement, delivery has occurred or services have been rendered, the sales price is fixed or determinable, and collectibility of the resulting receivable is reasonably assured. Revenues from product sales to customers other than distributors are recognized upon shipment or delivery depending on the terms of sale. Although our distributor has no price protection rights or rights to return product, other than for warranty claims, we defer recognition of revenue and related cost of revenues, on a gross basis, from our distributor until our distributor confirms an order from our customer.
In multiple element arrangements, we determine whether there is more than one unit of accounting. To the extent that the deliverables are separable into multiple units of accounting, we then allocate the total fee on such arrangements to the individual units of accounting based on verifiable objective evidence of fair value using the residual method. We recognize revenue for each unit of accounting depending on the nature of the deliverable(s) comprising the unit of accounting.
We offer product maintenance and repair arrangements to our customers. Amounts due from our customers under these arrangements are initially recorded as deferred revenues. The fees are recognized as revenue on a straight-line basis over the service period and related costs are recorded as incurred.
Revenues from the licensing of our design and manufacturing technology, which have been insignificant to date, are recognized over the term of the license agreement or when the significant contractual obligations have been fulfilled.
Warranty Accrual. We provide for the estimated cost of product warranties at the time revenue is recognized. While we engage in extensive product quality programs and processes, including actively monitoring and evaluating the quality of our component suppliers, our warranty obligation is affected by product failure rates, material usage and service delivery costs incurred in correcting a product failure. We continuously monitor product returns for warranty and maintain a reserve for the related expenses based upon our historical experience and any specifically identified field failures. As we sell new products to our customers, we must exercise considerable judgment in estimating the expected failure rates. This estimating process is based on historical experience of similar products, as well as various other assumptions that we believe to be reasonable under the circumstances. Should actual product failure rates, material usage or service delivery costs differ from our estimates, revisions to the estimated warranty liability would be required.
From time to time, we may be subject to additional costs related to warranty claims from our customers. This additional warranty would be recorded in the determination of net income in the period in which the additional cost was identified.
Inventory Valuation. We state our inventories at the lower of cost (principally standard cost which approximates actual cost on a first in, first out basis) or market. We record adjustments to our inventory valuation for estimated obsolescence or non-saleable inventories equal to the difference between the cost of inventories and the estimated market value based upon assumptions about future demand and market conditions. If actual market conditions are less favorable than those projected by management, additional inventory reserves may be required. Inventory write downs once established are not reversed until the related inventory has been scrapped or sold.
Impairment of Long-Lived Assets and Long-Lived Assets to be Disposed of. We account for the impairment of long-lived assets in accordance with Statement of Financial Accounting Standard, or SFAS, No. 144, "Accounting for the Impairment or Disposal of Long-Lived Assets". We evaluate the carrying value of our long-lived assets whenever certain events or changes in circumstances indicate that the carrying amount of these assets may not be recoverable. Such events or circumstances include, but are not limited to, a prolonged industry downturn, a significant decline in our market value or significant reductions in projected future cash flows.
Significant judgments and assumptions are required in the forecast of future operating results used in the preparation of the estimated future cash flows, including profit margins, long-term forecasts of the amounts and timing of overall market growth and our percentage of that market, groupings of assets, discount rates and terminal growth rates. In addition, significant estimates and assumptions are required in the determination of the fair value of our tangible long-lived assets, including replacement cost, economic obsolescence, and the value that could be realized in orderly liquidation. Changes in these estimates could have a material adverse effect on the assessment of our long-lived assets, thereby requiring us to write down the assets.
Accounting for Income Taxes. We adopted FIN 48 on December 31, 2006, the first day of the first quarter of fiscal 2007. FIN 48 prescribes a recognition threshold and measurement attribute for the financial statement recognition and measurement of a tax position taken or expected to be taken in a tax return that results in a tax benefit. Additionally, FIN 48 provides guidance on de-recognition, statement of operations classification of interest and penalties, accounting in interim periods, disclosure, and transition. As a result of the implementation of FIN 48, our tax assets and liabilities did not differ from the assets and liabilities before adoption; therefore, we did not record any adjustments as of the adoption date. In addition, consistent with the provisions of FIN 48, we reclassified $9.8 million of income tax liabilities from current to non-current liabilities because payment of cash is not anticipated within one year of the balance sheet date and we are unable to make a reasonably reliable estimate when cash settlement with a taxing authority will occur. At the adoption date of December 31, 2006, we had $16.7 million of total gross unrecognized tax benefit of which $14.0 million (net of the federal impact on state benefit) of unrecognized tax benefits would impact our effective tax rate if recognized. See Note 8â€”Income Taxes, for additional information.
We continue to recognize interest and penalties related to uncertain tax positions in income tax expense.
As part of the process of preparing our consolidated financial statements, we are required to estimate our income taxes. This process involves estimating our actual current tax exposure together with assessing temporary differences that may result in deferred tax assets. Management judgment is required in determining any valuation allowance recorded against our net deferred tax assets. Any such valuation allowance would be based on our estimates of income and the period over which our deferred tax assets would be recoverable. While management has considered taxable income and ongoing prudent and feasible tax planning strategies in assessing the need for a valuation allowance, if we were to determine that we would not be able to realize all or part of our net deferred tax assets in the future, an adjustment to the deferred tax assets would result in additional income tax expense in such period.
Given our increasing levels of profitability, we concluded that it is more likely than not that we will be able to realize all of our domestic deferred tax assets. For the deferred tax asset resulting from foreign net operating losses we have concluded that it is more likely than not that this asset will not be utilized and therefore, we have recorded a full valuation allowance for those deferred tax assets.
Results of Operations
Fiscal Years Ended December 29, 2007 and December 30, 2006
Our revenues for fiscal 2007 were primarily generated by sales of wafer probe cards to manufacturers of DRAM devices, which accounted for more than half of our revenue growth in fiscal 2007. The increase was driven by accelerated tooling cycles for probe cards as a result of our customers' continued migration to 70 nanometer nodes to reduce their cost of test and improve productivity, and by volume production ramps for 1 Gb devices. Additionally applications such as mobile RAM and graphic RAM contributed to our DRAM revenue growth. The increase in DRAM revenues was offset by a seasonal weakness in the mobile DRAM business due to decreased demand for mobile and consumer applications. In the fourth quarter, the increase in DRAM revenues was also offset in part due to early execution issues with our Harmony architecture-based DRAM products. Approximately 75% of our DRAM revenues for fiscal 2007 were derived from 80 nanometer and below technology products compared to 14% for fiscal 2006.
Revenues from sales to flash memory device manufacturers increased mainly due to increased demand for our NOR flash wafer probe cards by a significant customer whose high-volume ramp resulted from the growing demand for consumer applications which utilize multi-chip packages. Revenues generated from sales to flash memory device manufacturers also increased for our NAND flash wafer probe cards. Consumer applications which utilize multi-chip packages were a major driver for both categories of flash devices. Semiconductors that are integrated into multi-chip packages often benefit from increased wafer level testing to validate device performance before packaging.
Revenues from manufacturers of logic devices increased primarily due to the new technology node transition for area array flip-chip microprocessor products and existing and key customers engagements for our TrueScale applications in the mobile communications, digital consumer, and automotive controller markets.
Geographic revenue information is based on the location to which we send the customer invoices. For example, certain Korean customers purchase through their North American subsidiaries and accordingly, revenues derived from sales to such customers are reflected in North America revenues. The decrease in revenues in North America was due primarily to decreased sales related to product transitions combined with decreased customer demand resulting from new product delays. The increase in the percentage of revenues in Japan was primarily due to increased demand from one customer as a result of a major 70 nanometer and 1 GB tooling cycle. The increase in percentage of revenues in Asia Pacific was primarily due to growth in our business with Taiwan and Korean customers and strong demand related to 70 nanometer and 1 GB transitions. Revenues in Europe were primarily flat year over year as a percent of total revenue.
The increase in gross margin in fiscal 2007 compared with fiscal 2006 was primarily due to higher revenues combined with improved factory productivity, cost reductions and lower charges for inventory reserves which in turn improved gross margin percentage. These improvements were partially offset by higher warranty expense associated with the introduction of a new product technology and in the fourth quarter, by lower production levels. Excess custom probe card inventory write-downs decreased from $17.6 million or 4.8% of revenues in fiscal 2006 to $12.7 million or 2.7% of revenues in fiscal 2007 due to cycle time reductions, increase in yields and improvement in our order fulfillment process. Excess custom inventories are not uncommon for us as our advanced wafer probe cards are custom designs manufactured in low volumes and must be delivered on relatively short lead-times, which requires us to acquire production materials and start certain production activities based on estimated production yields and forecasted demand prior to or in excess of actual demand for our wafer probe cards. Gross margin for fiscal 2007 includes additional stock-based compensation expense of $5.4 million, or 1.2% of revenue, compared to, $4.3 million, or 1.2% of revenue for fiscal 2006, due to the adoption of FAS 123(R) in the first quarter of fiscal 2006.
Research and development expenses increased for fiscal 2007 as compared to fiscal 2006 primarily due to an increase in personnel, new technology, product development related costs and facility expansion. Personnel costs increased $6.1 million due to increased headcount while expenses related to new technology and product development increased $6.4 million. Facilities related costs and depreciation increased $1.8 million due to new investment in R&D equipment and facilities expansion at our Livermore facilities while stock-based compensation remained fairly consistent for the same periods. We are continuing the development of our next generation parallelism architecture and products, fine pitch memory and logic products, advanced MicroSpring interconnect technology and new process technologies. We are also making incremental investments in new technologies and products as we focus on new market opportunities.
Selling, general and administrative expenses increased for fiscal 2007 as compared to fiscal 2006 due to increases in expenses related to personnel costs, facilities expansion, outside legal and other professional fees and stock-based compensation. Personnel costs increased $10.2 million primarily due to increased headcount while facilities related costs and depreciation increased $0.8 million for fiscal 2007. Legal and other professional incurred for protecting our intellectual property portfolio, tax and accounting services, and other expenses increased $6.7 million. In addition, stock-based compensation expense also increased $3.3 million primarily due to increased headcount and the one-time modification charge of $1.4 million, incurred during the first quarter of fiscal 2007 resulting from the accelerated vesting of unvested stock options and restricted stock units in conjunction with the severance agreement of our company's former President.
The increase in interest income was due to larger cash, cash equivalents and marketable securities balances throughout fiscal 2007compared to fiscal 2006 while yields remained relatively flat. Cash, cash equivalents, restricted cash and marketable securities increased to $572.3 million at December 29, 2007 compared to $494.6 million at December 30, 2006. Other income for both fiscal 2007 and 2006 was mainly comprised of foreign currency gains, primarily related to Japanese Yen, and other expense.
MANAGEMENT DISCUSSION FOR LATEST QUARTER
Results of Operations
Three and Nine Months Ended September 29, 2007 and September 30, 2006
Revenues increased 29.5% and 26.3% in the three and nine months ended September 29, 2007 compared with the three and nine months ended September 30, 2006. Volume increases resulting from strong market demand for our advanced wafer probe cards continued in the third quarter of fiscal 2007 due to a variety of factors, including bit and design growth as semiconductor manufacturers transition to 70 nanometer nodes and 1 Gb devices, combined with strong growth in the demand for NOR flash memory by mobile device manufacturers.
Our revenues for the three and nine months ended September 29, 2007 were primarily generated by sales of wafer probe cards to manufacturers of DRAM devices. The increase was driven by accelerated tooling cycles for probe cards as a result of our customersâ€™ continued migration to 70 nanometer nodes to reduce their cost of test and improve productivity, and by volume production ramps for 1 Gb devices. The increase in DRAM revenues was offset by a seasonal weakness in the mobile DRAM business due to decreased demand for mobile and consumer applications. Approximately 81% and 71% of our DRAM revenues for the three and nine months ended September 29, 2007 were derived from 80 nanometer and below technology products compared to 17% and 9% for the three and nine months ended September 30, 2006.
Revenues from sales to flash memory device manufacturers increased mainly due to increased demand for our NOR flash wafer probe cards by a significant customer whose high-volume ramp resulted from the growing demand for consumer applications which utilize multi-chip packages. Semiconductors that are integrated into multi-chip packages often benefit from increased wafer level testing to validate device performance before packaging.
Revenues from manufacturers of logic devices increased primarily due to a key customerâ€™s ongoing transition to advanced technology nodes in both chipset application and high performance flip chip microprocessors which are used in personal computer, gaming and graphics applications.
Geographic revenue information is based on the location to which we send the customer invoices. For example, certain Korean customers purchase through their North American subsidiaries and accordingly, revenues derived from sales to such customers are reflected in North America revenues.
The increase in Japan revenues for the three and nine months ended September 29, 2007 as compared to the same period in the prior year was primarily due to increased mobile DRAM demand directly related to implementation of 70 nanometer tooling cycles combined with increased growth in our customer base in our NOR flash and logic business. The increase in Asia Pacific for the three months ended September 29, 2007 as compared to the same period in the prior year was primarily due to increased DRAM shipments. Asia Pacific revenue remained relatively, as a percentage of revenue, was flat for the nine months ended September 29, 2007 as compared to the same period in the prior year. The decrease in revenues in North America for the three and nine months ended September 29, 2007 compared to the same period in the prior year was primarily driven by decreased demand for NAND flash and NOR flash products related to product transitions and new product delays. The increase in revenues in Europe for the three and nine months ended September 29, 2007 was primarily due to the increased demand for DRAM and Logic devices in this region.
Gross margin increased for the three and nine months ended September 29, 2007 compared with the three and nine months ended September 30, 2006 due to increased revenues and direct and indirect labor productivity improvement. The labor productivity improvement was partially offset by an increase in material and warranty cost arising from the introduction of new product technology into manufacturing. In addition, gross margin improved as a result of lower inventory write-offs of, which was $9.5 million, or 2.8% of revenues compared to $12.0 million or 4.4% of revenues for the nine months ended September 29, 2007 and September 30, 2006, respectively. The lower inventory write-offs was primarily due to cycle time reductions, increase in yields and improvement in our order fulfillment process. Stock-based compensation expense increased $0.8 million and $1.1 million for the three and nine months ended September 29, 2007 compared to the same period in the prior year due primarily to increased headcount.
Research and development expenses increased for the three and nine months ended September 29, 2007 as compared to the same period in the prior year primarily due to an increase in personnel, new technology, product development related costs and facility expansion. For the three and nine months ended September 29, 2007, personnel costs increased $1.6 million and $4.6 million, respectively, due to increased headcount while expenses related to new technology and product development increased $2.2 million and $5.1 million, respectively. Depreciation increased $0.6 million and $1.4 million respectively due to new investment in R&D equipment and facilities expansion while stock-based compensation remained fairly consistent for the same periods. We are continuing the development of our next generation parallelism architecture and products, fine pitch memory and logic products, advanced MicroSpring interconnect technology and new process technologies. We are also making incremental investments in new technologies and products as we focus on new market opportunities.
Selling, General and Administrative
Selling, general and administrative expenses increased for the three and nine months ended September 29, 2007 compared to the same periods in the prior year primarily due to increases in expenses related to personnel costs, facilities expansion and outside legal services. For the three and nine months ended September 29, 2007 personnel related costs increased by approximately $2.8 million and $8.4 million, respectively, primarily due to increased headcount. Facilities expansion costs for the same period increased $0.4 million and $1.3 million, respectively, while combined outside legal services incurred for protecting our intellectual property portfolio, tax services and other expenses increased by approximately $0.8 million and $3.4 million, respectively. In addition, stock-based compensation expense also increased $0.1 million and $3.3 million for the three and nine months ended September 29, 2007 primarily due to increased headcount and the one-time modification charge incurred during the first quarter of fiscal 2007 resulting from the accelerated vesting of unvested stock options and restricted stock units in conjunction with the severance agreement of the Companyâ€™s former President.